NES-101 Top-Loader Repair Reference

The NES-101 is Nintendo’s 1993 redesign, the “New-Style NES,” the one where the cartridge drops into a slot on top. It looks like a cost-reduced afterthought, and in some ways it is, but it is a clean little machine to work on once you throw out the habits the front loader taught you. This page is the companion to my NES front-loader reference: the shared internals (the 2A03 CPU, the 2C02 PPU, the 72-pin bus signals) live over there. What follows is the delta, the handful of things that make the top loader diagnose differently.

It is written for someone comfortable opening the console and using a multimeter. Because no OEM Nintendo service manual or schematic for the NES-101 was ever published or scanned, the electrical detail here rests on the community’s reverse-engineered board (OpenTendo, an open-hardware KiCad project) cross-checked against board photos and the repair record. I flag anything that rests on a single source.

Almost every unit you will meet is the common board, silkscreened NESN-CPU-01. Two rare later revisions (NESN-CPU-JIO-01/02 and NESN-CPU-AV-01) relocated the CPU and PPU and fixed the video; the PAL top loader (NESP-101) is built on the JIO board. If you pull the shield and the CPU and PPU are transposed with one extra custom chip where the small logic ICs should be, you have a revised board and some of what follows does not apply. Everything below is verified against the plain NESN-CPU-01 unless I say otherwise.

Two reflexes to unlearn from the front loader

Before the symptom list, two facts that change how you read the console.

First, there is no lockout chip. The NES-101 has no 10NES/CIC, no CIC oscillator, and in fact no power LED at all. That means the famous once-per-second blinking light simply cannot happen here, because there is nothing to generate it. A dirty or failing cartridge contact, which on a front loader gives you that blink loop, on a top loader gives you a black screen, garbage tiles, or a freeze instead. Never read “solid picture-less screen, no blink” as “so it is not a connector problem.” It usually still is.

Second, the vertical “jailbars” in the picture are stock behavior, not a fault. They are a board-layout flaw, and no repair removes them. More on that below.

Common problems and fixes

Won’t boot, black screen, garbage graphics, or a freeze

With no lockout chip in the way, a top loader that will not boot is a real fault, and the first thing to prove is the cartridge contact. The connector here is a soldered, non-ZIF edge connector, closer to an ISA slot than to the front loader’s spring-loaded ZIF sled, so it does not suffer the front loader’s pin-fatigue mode. It does still collect oxide and debris. The top-loading throat is an open slot and acts as a trap for dust and grime.

Try a known-good cartridge whose edge you have just cleaned with high-purity (91 percent or better) isopropyl alcohol. If a clean, known-good cart still misbehaves, clean the slot: a degreaser pass on cartridge-connector cleaning tools to cut the grime, then an alcohol pass to remove the residue. That clears the large majority of no-boot and intermittent-boot complaints.

What this connector is not is wear-proof. Community sources market it that way, and it is genuinely better than the ZIF, but it still corrodes (I have seen the record of ones gone completely green inside), can trap enough debris to block a cart from seating, and occasionally takes bent pins. It is a real replacement item, just an uncommon one. If you do replace it, read the pitch warning in the parts section first: it is 2.5 mm, not the industry-standard 2.54 mm, and generic parts do not fit.

Vertical jailbars or washed-out color on RF

Solid-color backgrounds show faint vertical banding, and the color looks muddy. This is not a fault you can repair, and chasing it as one wastes time and parts. The cause is the board layout: the thin trace carrying composite video from the PPU is bundled with digital lines including the PPU’s address bus, and the digital switching couples into the video.

The important thing on the bench is what it is not. It is not a power or capacitor problem. Someone ran an NES-101 from a clean 5 V switching supply with the entire rectifier and regulator section removed, and the RF output was unchanged. So do not sell a recap or a fresh power supply as a video fix; it will not touch the bars. It is also not a bad RF modulator: the design-sibling AV Famicom has the same banding and no RF modulator at all.

The only real cure is to take the video off the PPU before it reaches the board copper, which is the composite AV mod covered under Mods. On the common board that mod is close to mandatory if you want a sellable picture. The rare revised boards fixed the layout at the factory, so identify the revision before you quote anyone for the work.

Noisy or degraded video and audio, hum, snow

If the picture and sound are present but degraded, with hum, snow, or general flakiness, the suspect is C13, the 1500 uF / 25 V reservoir capacitor after the bridge rectifier. Sources that have modded these in volume single it out as the one electrolytic that actually fails on this console: game-tech reports replacing “at least 50 of these over the years” and says only two of the five electrolytics have ever caused them problems. I have not independently confirmed that failure rate on my own bench yet, so I treat it as a community observation rather than a rule: I check C13 before I condemn it (ESR and capacitance out of circuit, or ripple on the 7805 input in circuit) and replace it when it actually reads bad. A useful soft test is to run the unit a long while with intermittent power cycling; a marginal cap improves as it warms, a dead one never does.

One gotcha when you order: the silkscreen at C13 reads 1000 uF, but the parts actually fitted were 1500 uF. Fit 1500 uF / 25 V. (The silkscreen legend itself is a single-source claim; the value to fit is not in doubt.)

Intermittent boot needing several resets, and a hot 7805

The 7805 regulator on this board fails soft, and it fails in a way that will fool you if you test it wrong. A failing one reads a clean 5 V out of circuit while unloaded, then sags (one documented case measured about 3.6 V) once it is under load. The discriminator is load, not whether the part is in or out of the board: the repair log that documents this reproduced the droop with an out-of-circuit bench load of roughly 200 mA. So measure the rail under the console’s own load at the regulator’s output pin, and if you bench-test a suspect part, load it.

Two cautions before you condemn the regulator. First, a hot 7805 with a low rail is equally consistent with a short downstream pulling it into current limit; another NES-101 sat at about 2.7 V and cooked several good regulators before the owner found the real fault was a short, not the 7805. So power off and check the resistance from the 5 V rail to ground first (a healthy board is a couple hundred ohms, not a dozen). Second, despite how memorable the soft-failure is, the 7805 is not the most common electrical fault on this console; C13 is, per the only frequency data anyone has published. A sagging rail is a boot problem, not a chip-killer: in the documented case the CPU and PPU were fine right after the regulator swap.

Dead or intermittent reset or power switch

If the reset button or power switch works “once or twice” and then not, that is oxide inside the switch, not a board fault, and it is worth ruling out before you go looking at the reset circuit. Flood the switch through the seam between its white and black plastic halves with contact cleaner, actuate it a few dozen times, re-spray, and let it dry fully before powering up. Cleaning usually wins; replacement switches exist if it does not.

No RF picture, audio fine

A snowy, rolling, or absent RF picture with working sound is often just the corroded channel 3 / channel 4 select switch. Work it back and forth and retest before you suspect anything on the board.

One controller port dead, or wiggling the plug changes it

Cracked solder joints at the controller-port assembly, from years of insertion and removal stress, are a known NES-101 failure. Flex-test the port with the board out, inspect the through-hole joints under magnification, and reflow them. If the port took a surge, check its protection diode arrays (DAN601 and UPA64H) as well.

Sound but no picture on an unmodded unit

If a stock unit has audio and a black screen, suspect the single video-amp transistor, Q1 (a 2SA937 PNP), or the resistor network around it. Probe the PPU’s video pin for signal, then check Q1’s output into the RF modulator. Q1 has good substitutes (BC856/857/858, BC807, or a 2N3906 in the mod circuit), so a dead one is cheap to fix.

Used units: assume a soldering iron has already been in there

By 2026 a used top loader has more likely than not already had the AV mod attempted, so before you diagnose a manufacturing defect, look for prior work. The tells: sound but no picture with flux and wires near the PPU (a botched pin-21 lift, or a cooked pin), a picture that streaks sideways off bright edges (a mod transistor installed with emitter and collector swapped, because the two common substitutes have different pinouts in the same package), jailbars that survived an AV mod (video tapped from the pad instead of the lifted pin, so it bought nothing), or an empty Q1 footprint with cut traces (a prior owner harvested Q1 for the mod amp). None of those are board faults; they are fingerprints.

Internal corrosion under the connector

Liquid that gets in through the cart throat corrodes traces underneath the 72-pin connector, out of sight, and shows up as no video or garbage on a board that looks clean. Continuity-check the cart-slot pins through to the CPU, PPU, and RAM. Fix with bodge wires or a conductive trace pen; worst case, lift the connector to repair underneath. I neutralize active corrosion, clean with isopropyl alcohol, and seal the treated area, the same process in my restoration and testing writeup.

Bench warning worth repeating

Do not power the board up with any electrolytic lifted, and do not “test” it mid-recap. In the one documented case, an owner did exactly that after an otherwise successful 7805 repair, and both the CPU and PPU cooked and failed short. This rests on a single repair log, and the proposed mechanism (a voltage spike from missing output filtering) is the poster’s own hedged hypothesis, never scoped or reproduced, and it sits slightly at odds with the regulator’s own datasheet. But there is zero upside to powering a half-recapped board, and the CPU and PPU are the two irreplaceable parts, so treat it as free insurance.

Inside the NES-101

A quick tour of what makes the top loader diagnose differently from the front loader. The shared CPU/PPU internals are on the front-loader page.

No lockout, no LED. There is no 10NES/CIC chip, no separate CIC oscillator, and no power indicator light of any kind. This is why the blink loop cannot occur and why the console happily runs unlicensed and out-of-region cartridges (a PAL game runs, just at NTSC timing). Reset here is a plain switch pulling the reset line low, not a function of the lockout chip as it is on the front loader.
RF only, from the factory. The PPU drives one PNP transistor straight into the RF modulator; there is no composite buffer and no AV jack. Composite output is a mod on this console, not something already present. (Only the extremely rare AV-01 board has a real multiout.)
The jailbars are baked into the layout, as above, not into the power supply.
No audio amplifier. The two APU audio pins are mixed by a passive resistor network into the RF modulator; there is no active audio stage. One consequence is that the expansion-audio mixing resistor differs from the front loader’s, because there is no amplifier to feed (see Mods).
Power comes in as 9 V AC through the same OEM adapter the front loader uses (the bridge rectifier is on the board, not in the brick), so barrel polarity is a don’t-care on a stock unit, and a regulated 9 V DC supply works too. The 7805 sits on a real heat sink here, which the front loader lacks.
The cartridge connector is soldered and non-ZIF, populates only 68 of its 72 positions (four pins have no metal at all), and repurposes the four old lockout pins: two float, one carries +5 V, one carries a PPU data line. If you are used to the front loader, measuring 5 V on cart pin 70 is normal here, not a fault.

Mods worth knowing

I do not reproduce anyone’s install guide, schematic, or board art here. Several of the best references are open-hardware or otherwise licensed work that belongs to its authors; I link those rather than copy them. This is an overview of what is worth doing and where the real instructions live.

Composite AV mod (the jailbar fix). The defining top-loader mod, and close to mandatory for resale, since it both adds composite-plus-audio output and clears the jailbars. The whole trick is isolating PPU pin 21 (the video output) so the video leaves the chip before it can pick up board noise; tapping the pad instead of the lifted pin keeps the bars. On a resale-grade unit I favor socketing the PPU so the lift is reversible and future-proofs an RGB or HDMI install. The circuit is a small PNP emitter follower; watch the transistor pinout, because 2SA933 is E-C-B and 2N3906 is E-B-C and swapping them without rotating streaks the picture. Kits: CatHouse Games (about $10), Voultar’s amp board, and RetroFixes' NES-101 board (about $35). The canonical community schematic and full procedure are on the Console5 NES-101 wiki and ConsoleMods: Top Loader AV Mod; I link those rather than reprint their drawing.
RGB output: NESRGB. Tim Worthington’s board regenerates the video for RGB, S-video, and composite with no lag. On the top loader it needs a pin-adapter board and follows the AV Famicom install, not the front-loader one; the classic mistake is reset polarity (the top loader wants the negative setting). Unlike the front loader, it does not need a supplementary regulator, because the top loader already has the larger heat sink. Reference: etim.net.au NESRGB.
HDMI: Hi-Def NES. Kevtris’s kit gives a lag-free digital picture and audio and even synthesizes expansion audio in the FPGA. It is discontinued and secondhand only, so price accordingly. Reference: game-tech Hi-Def NES.
Expansion audio. Because the cart connector is missing the expansion-audio pin and there is no amplifier in the audio path, restoring Famicom mapper audio (FDS, VRC6, and similar) takes a console-side resistor from the surviving expansion pin (cart pin 51) into the audio node, plus a cart-side bridge. The value that circulates for a stock top loader is 1.2k, which is much smaller than the front loader’s 47k precisely because the top loader has no amplifier to drive. I want to flag that the 1.2k is a single-source, by-ear value from one forum thread, the value is genuinely contested (into an NESRGB people use 47k instead), so treat it as a starting point to dial in, not a spec.
OpenTendo replacement board. When a board is beyond saving (acid damage, lifted traces, a wrecked mod), the OpenTendo-TopLoader project is a 1:1 open-hardware recreation of the NESN-CPU-01 board you can have made and populate with donor parts plus an original CPU and PPU. It is deliberately not an upgrade, so it jailbars exactly like the original. It is released under the TAPR Open Hardware License; I link the repo rather than mirror its files. Reference: OpenTendo-TopLoader.

Some front-loader mods do not apply here at all: there is no lockout chip to disable (and no blink loop to cure), the ZIF-connector replacements do not fit the soldered non-ZIF slot, there is no bottom expansion port for ENIO/EPSM-style accessories, and composite output is a mod to add rather than something to tap.

For a broader mod orientation, RetroRGB’s NES mods index is the best single jumping-off page.

Recap and parts

The whole board carries exactly five electrolytic capacitors; everything else is ceramic. So a top-loader “recap” is a light job, and realistically it is a C13 job. Community sources single out C13 (the 1500 uF / 25 V reservoir after the bridge) as the one that actually fails, and I treat that as their observation pending my own bench data: I do the other four because the board is already open and a kit is cheap, not because they are likely bad. Remember to fit 1500 uF at C13 even though the silkscreen says 1000 uF, and remember that recapping does not touch the jailbars.

A few practical notes:

7805 regulator. A plain L7805CV (TO-220, 1 A) drops in and keeps the OEM heat sink. If you want to kill the heat, use a 1.5 A switching drop-in such as the Murata OKI-78SR-5/1.5. Do not reach for the 500 mA 7805SR-C that older writeups recommend; the console can draw 400 to 600 mA at 5 V, which is at or over that part’s rating before you add any mod.
72-pin connector. If you must replace it, it is 2.5 mm pitch, not 2.54 mm. Generic “NES 72-pin” parts flooding the marketplace are the front-loader NES-001 part and will not solder into this board (they run about 1.4 mm out of register across a row). Harvest from a dead NES-101 or from a Game Genie, which carries a correct 72-pin connector, and dry-fit before you commit solder, because seat height in the top-loader shell is not well documented even at the right pitch.
CPU and PPU. The RP2A03 and RP2C02 are the only two custom, irreplaceable chips. A donor pull is the only 100 percent correct option; the UMC clone equivalents (UA6527 CPU, UA6528 PPU) work but have documented audio and compatibility differences (the clone PPUs, for instance, break Everdrive savestate restore), so I do not consider them resale-grade. If you are pulling either chip, socket it.
Donor economics. One dead NES-101 covers the whole donor-only list at once (cart connector, controller ports, both switches, the input choke) plus the parts that are merely inconvenient to buy. For a fleet, a scrapped top loader is often worth more as a parts donor than as a repair.

Everything in this section is grounded in the OpenTendo BOM and the community wikis; because no OEM NES-101 schematic exists, treat OpenTendo’s reverse-engineered part values as high-quality but community-tier, and measure before you rely on a borderline one.

If you would rather buy a console that has already had this work done, or you need a tested cartridge to go with it, everything I restore is in the shop. (I will link specific NES-101 service, AV-mod, and recap listings here as those pages firm up.)

The hard data behind all of the above (the cap map with substitutes, the non-cap consumables, the chip and connector pinouts, and the schematic facts) is tabled in the sections that follow. Long per-item notes fold away to keep it readable; expand any of them for the full detail. Read the confidence tags: no OEM NES-101 schematic was ever digitised, so a good deal of this rests on the OpenTendo reverse-engineered board file, and I have marked it accordingly.

Capacitor lists

The five electrolytics, per revision, with the substitutes I fit. Expand any row’s notes for the per-cap detail, including why C13 is the one everyone talks about.

NESN-CPU-01 NESN-CPU-01: NTSC NES-101 (1993-95, the overwhelming majority)

Mainboard — electrolytics

Desig	Value	V	Substitute	Note
C1	100µF	6.3V	Panasonic ECE-A0JKA101I (100µF/6.3V, 5 mm dia, 2.5 mm pitch)	bulk decoupling on the +5V rail ^✓^{console5-101,opentendo-sch,gametech-mods}
notes on C1 Do not read substitute part numbers as OEM specs. Game-tech’s own NES-101 kit ships a 35 V part in this position. Stock is 6.3 V.
C3	1µF	50V	Nichicon UVR2A010MDD1TD (a 100 V part: deliberately over-rated)	audio mixer output coupling, feeding FC1 → P6 pin 3 ^✓^{console5-101,opentendo-sch}
notes on C3 This is the AC coupling cap on the passive audio mix. If audio is thin or missing but the R6/R7 legs measure right, this is the part between them and the RF connector.
C11	0.47µF	50V	Nichicon UVP1HR47MDD1TD	reset-switch debounce, across P3 on the /RST net ^✓^{console5-101,opentendo-pcb}
notes on C11 The board netlist puts this cap on the /RST net with the reset switch P3 and CPU pin 3. It is the reset debounce. A shorted C11 or a dirty reset switch will hold the CPU in reset, which on a lockout-free console is one of the few ways to get a dead-but-powered board.
C13	1500µF	25V	Rubycon 25YXS1500MEFC12.5X20 (12.5 x 20 mm can)	raw-rail reservoir after the DB1 bridge: sources call this the one that actually fails ^✓^{console5-101,opentendo-sch,gametech-mods}
notes on C13 Two things to carry off the bench with this one. It stays charged with the console switched off. C13 sits upstream of the power switch, so flipping the switch does not discharge it. Discharge before probing. The failure-rate claim is theirs, not mine. game-tech, writing from dozens of broken NES-101s, says only two of the five electrolytics have ever caused problems and that “the main problem cap is in the power circuit, i’ve replaced at least 50 of these over the years”. That is a good frequency datapoint from someone working in volume, and I am repeating it as their finding: I have not accumulated the units to confirm or contradict it. The silkscreen reportedly lies. Console5 says the silkscreen reads 1000 µF but only 1500 µF parts were fitted. That specific claim is Console5 alone and the board photos do not resolve the legend. What is not in doubt is what to fit: 1500 µF / 25 V, agreed by Console5, the OpenTendo BOM and third-party cap sets. Check can height: the shell clears the OEM 12.5 x 20 mm can, but not much more. And a recap is not a video fix. game-tech stripped the entire power section out and fed the board clean +5 V from a switching brick, and the jailbars were unchanged. Do not sell it as one.
C14	1µF	50V	KEMET ESS105M050AB2EA	7805 output cap, directly on the +5V rail ^✓^{console5-101,opentendo-sch}
notes on C14 Worth knowing when you read the “never power the board with a cap lifted” warning: this cap sits on the regulator’s OUT node independently of C1, and the ST L78xx datasheet says outright that no output capacitor is needed for stability. That weakens the proposed oscillation mechanism behind that warning, but the bench rule still costs nothing.

NESP-101 NESP-101: PAL top loader (NESN-CPU-JIO-02 board, Australia / New Zealand)

Board p/n: NESN-CPU-JIO-02

Replacement parts

The non-cap parts an NES-101 repair actually goes through, and for the 72-pin connector, the measurement to take before you order one.

Non-cap consumables

Function	OEM part	Why replaced	Substitute	Note
72-pin cartridge connector (P1)	2.50 mm pitch, 68 contacts populated, soldered through-hole	corrosion, trapped debris, occasionally a bent pin: not spring fatigue	harvest from a donor NES-101 or a Game Genie; 2.50 mm parts exist on AliExpress	NEVER order a generic 2.54 mm 72-pin part: it will not even solder in ^✓^{nesdev-t23781,nesdev-t7449,gametech-intro,consolemods-pin}
notes Free pre-solder test before you commit: centre of pin 1 to centre of pin 36 must measure 87.5 mm. A 2.54 mm part measures 88.9 mm and runs about 1.4 mm out of register across the row. A Game Genie is a cheap donor for a correct-pitch connector and gets recommended independently a decade apart on NESdev. There is a second reason not to substitute a generic part: slot thickness. One NESdev regular’s warning about the 2.54 mm parts people recommend is that they seem fine “until you rub all the copper off of your games”: a connector that grips too hard abrades cart contacts. Height and seating in the NES-101 shell are unverified even on correct-pitch aftermarket parts. Buy two and dry-fit before you solder.
Bridge rectifier (DB1)	Rectron RC203, 200 V 2 A, RC-2 package	sources say a tired bridge shows as hum bars in video and audio	any 2 A RC-2 bridge; Console5 sells a 2W04G-E4/51 as the explicit RC203/RC204 substitute	NESN-CPU-01 only: the JIO boards use two diode arrays instead ^{single source}^{console5-101,opentendo-sch,gametech-power}
notes The hum-bars-to-bridge inference is Console5’s alone; the RC203 identification is separately confirmed. Mind the forward drop when you substitute: game-tech measured 1.1 V across the OEM part and NESdev gives 1.2-1.4 V, and that is what sets the ~8.2 V minimum usable DC input.
+5V regulator (U9 on -01, U7 on JIO/AV)	7805, TO-220, heat-sinked	sagging rail under load: browns out the CPU/PPU	ST L7805CV or any 1 A 7805; keep the heat sink	test it IN CIRCUIT or under a ~200 mA bench load: it reads fine unloaded ^{single source}^{st-l78xx,nesdev-t17501,opentendo-sch}
notes The frequency claim that this is the dominant NES-101 failure is not supported by anything I have found. The only volume datapoint in my sources points at C13 instead. What NESdev t=17501 does establish is the test method: the owner measured ~3.6 V in circuit with a plain meter (the console being the load) and reproduced the droop out of circuit only once he added a ~200 mA bench load. Rule out a downstream short first. A healthy NES-001 reads about 255 Ω from +5 V to GND; a board that reads ~350 mA draw with a swapped regulator “to no avail” was shorted elsewhere.
Video output transistor (Q1)	2SA937 PNP, TO-92	no picture with a good rail and a good clock	2N3906 works but has a DIFFERENT lead order: 2SA937 is E-C-B, 2N3906 is E-B-C	game-tech has seen factory-repaired units where Nintendo replaced both Q1 and Q2 ^✓^{nesdev-ppu,gametech-intro,rohm-2sa937}
notes If you are doing an AV mod, do not throw this transistor away. NESdev’s recommended composite amplifier reuses the original 2SA937 rather than adding a new one.
Master-clock oscillator transistor (Q2)	2SC2021 NPN	dead clock: perfect +5V rail, completely dead console	2SC2021, purchasable; it is not a harvest-only part	check the clock at cart pin 37 or CPU pin 29 before condemning the CPU ^{single source}^{opentendo-sch,gametech-intro}
notes OpenTendo’s release notes list the 2SA937, the 2SC2021 and the DAN601 / UPA64H diode arrays as buyable, which corrects the common assumption that they are donor-only. The genuinely harvest-only parts on this board are the controller ports, the cartridge port, the reset button, the power switch and the T1 coil.
CPU / PPU (U6 / U5)	RP2A03G or -H / RP2C02G-0 or -H-0	the only unobtainium silicon on the board: no OEM stock since ~1999-2002	donor pull, or UMC clones: UA6527 CPU / UA6528 PPU (UA6527P / UA6538 for PAL)	clone CPU has swapped pulse duty cycles; every clone PPU has unreadable OAMDATA and palette RAM ^✓^{console5-101,opentendo-sch,nesdev-t17501}
notes Do not treat a G-suffix as an authenticity check. RP2A03G ran to Nov 1993 and RP2C02G-0 to Oct 1993, with the H revisions taking over from Dec 1993, and the NES-101 shipped Aug 1993 through 1995, so late top loaders legitimately carry H parts. The clone PPU defect matters commercially: unreadable OAMDATA and palette RAM breaks flashcart savestate restore, which is exactly what a buyer who cares enough to own an Everdrive will notice. If you are pulling either chip, fit sockets. OpenTendo specs an On Shore ED40DT DIP-40, which is a stamped dual-wipe part: for silicon this irreplaceable I would rather pay up for machined pins.
Reset switch (P3)	OEM tactile switch, harvest-only	worn or dirty contacts can hold /RST low: dead-but-powered board	donor NES-101; no drop-in aftermarket part I trust	on a lockout-free console a stuck reset is one of the few ways to get a black screen with a good rail ^{single source}^{opentendo-pcb,console5-101}
notes The reset path is a plain switch with a 0.47 µF debounce cap (C11) into CPU pin 3. There is no CIC, so there is no 1 Hz reset generator and the front loader’s blinking-power-LED reboot loop cannot happen here. If a top loader resets repeatedly, it is a real fault: a shorted C11, a dirty switch, or a browning-out 5 V rail.

Chip & connector pinouts

The component library: each IC and connector defined once, with an interactive pin diagram and a folded pin table. The revision badge on each card shows which board it applies to. The 72-pin cartridge connector is the one to expand first: it carries the repurposed ex-CIC pins and the four contacts that are physically missing on this console.

Components & pinouts

Each part is defined once. The revision badge on every card shows exactly which board revision(s) it applies to.

Every diagram rotates and flips to match the board in front of you, zooms from a whole-package overview up to 3.2×, and saves at the orientation you are looking at — ↓ SVG matches the screen, and ↓ SVG (print) gives you the same drawing as ink on white. Both are vector, so print them at any size you like, which is the better route for the long connector pinouts since printing this page has to shrink them to fit the sheet. The # beside a part name links to that card, and the one in the pin panel links to a single pin — either link opens the card for whoever you send it to.

Bridge rectifier DB1: Rectron RC203 (200 V, 2 A, RC-2 package) NESN-CPU-01 header-4^{single source}^{opentendo-pcb,opentendo-sch,console5-101}#

on-board rectification: this part is why the barrel polarity does not matter. The JIO boards do not have it

Sources say a tired bridge shows up as hum bars in video and audio, which is Console5’s line on its cap-kit page and is the one inference only they make. The RC203 identification itself is separately confirmed by the OpenTendo BOM and by Rectron.

Note the OEM grade is 200 V. RC204 is the 400 V part in the same family and is what most substitutes are; electrically irrelevant at 9 VAC, but 400 V is not “the” OEM spec. Any 2 A RC-2-footprint bridge works: the real constraints are the footprint and the 1.1-1.4 V forward drop the 7805 headroom budget assumes.

0° 1×

Click a pin to see its signal, net, and sources.

Interactive diagram needs JavaScript. The full pinout is in the table below.

Pin	Signal	Cat	Net	Note
1	+ (DC out)	rail	vraw	into C13 and the power switch ^{single source}
2	- (GND)	gnd	gnd	^{single source}
3	AC in	rail	acin_t1a	from T1 ^{single source}
4	AC in	rail	acin_t1b	from T1 ^{single source}

Custom Nintendo PIO (JIO) BU3266S / BU3270S NESP-101 dip-32^{single source}^{console5-bu3270,consolemods-models,nerdly}#

U3 on the JIO boards: swallows the 74LS139 decoder AND both 74HC368 controller buffers

This is the chip that defines the redesigned board. On a plain NESN-CPU-01 you have three DIP logic chips clustered by the controller ports (U3 74LS139 plus U7/U8 74HC368); on a JIO board there is one 32-pin custom in their place. Nintendo introduced it on the AV Famicom (HVCN-CPU-01) and back-ported it into the top-loader revision.

Both BU3266 and BU3270 turn up in the wild, so do not treat BU3270S as the JIO part number: Nerdly Pleasures specifically places BU3266 in the Australian PAL top loaders, and the BU3270S-to-NESN-CPU-AV-01 assignment rests on Console5 alone.

Confidence caveat on the table below: Console5’s page and the NESdev BU3266/BU3270 page both reproduce the same Jacques Gagnon nes_pio_pinout.txt, so they are one source, not two. Gagnon himself flags pins 2/30/31 as unknown and guesses they might be P0-D2/D3/D4. Treat this as a starting map for probing, not as a datasheet.

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Click a pin to see its signal, net, and sources.

Interactive diagram needs JavaScript. The full pinout is in the table below.

Pin	Signal	Cat	Net	Note
1	GND	gnd	gnd	^{single source}
2	NC	nc		Gagnon: unknown, possibly P0-D2 ^{single source}
3	M2	signal	m2	^{single source}
4	A15	bus	abus	^{single source}
5	A14	bus	abus	^{single source}
6	A13	bus	abus	^{single source}
7	P1-D0	signal	p1d0	port 2 data ^{single source}
8	P0-D0	signal	p0d0	port 1 data ^{single source}
9	P1-D1	signal	p1d1	^{single source}
10	P0-D1	signal	p0d1	^{single source}
11	P1-D2	signal	p1d2	^{single source}
12	+5V	rail	vcc	^{single source}
13	P1-D3	signal	p1d3	^{single source}
14	P1-D4	signal	p1d4	^{single source}
15	GND	gnd	gnd	^{single source}
16	INV-1I	signal	inv1i	audio inverter input ^{single source}
17	INV-1O	signal	inv1o	audio inverter output ^{single source}
18	D4	bus	dbus	CPU data bus ^{single source}
19	D3	bus	dbus	^{single source}
20	D2	bus	dbus	^{single source}
21	/INP1	signal	oe2	$4017 read strobe ^{single source}
22	/INP0	signal	oe1	$4016 read strobe ^{single source}
23	D1	bus	dbus	^{single source}
24	D0	bus	dbus	^{single source}
25	INV-2O	signal	inv2o	PA13 inverter output ^{single source}
26	INV-2I	signal	inv2i	PA13 inverter input ^{single source}
27	CS (U1)	signal	wram_ce	work-RAM chip select ^{single source}
28	/DBE	signal	ppu_ce	PPU chip select ^{single source}
29	/ROMSEL	signal	romsel	^{single source}
30	NC	nc		Gagnon: unknown, possibly P0-D3 ^{single source}
31	NC	nc		Gagnon: unknown, possibly P0-D4 ^{single source}
32	+5V	rail	vcc	^{single source}

Controller port 1 buffer (hex inverting 3-state) TC40H368P (Toshiba) / SN74HC368N NESN-CPU-01 dip-16^{single source}^{opentendo-pcb,console5-101}#

U7 ('CI'): puts port 1's D0/D3/D4 onto the CPU data bus when $4016 is read

This is the chip to suspect when one controller port is dead and the other is fine. The buffer is gated by /OE1 (the $4016 read strobe) on pin 1, and the same /OE1 line is what leaves the board as the port’s CLK pin, so if pin 1 is dead, the controller never gets clocked and nothing gets read back.

Pins 10, 12 and 14 sit on +5 V as buffer inputs whose inverted outputs drive CPU D1 and D2 low during a port read. Absorbed into the JIO chip on the redesigned boards.

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Interactive diagram needs JavaScript. The full pinout is in the table below.

Pin	Signal	Cat	Net	Note
1	/OE1	signal	oe1	buffer enable: $4016 read strobe from CPU pin 36 ^{single source}
2	P1 D0 in	signal	p1_d0	from port 1 pin 4 ^{single source}
3	CPU D0	bus	dbus	^{single source}
4	P1 D3 in	signal	p1_d3	from port 1 pin 6 ^{single source}
5	CPU D3	bus	dbus	^{single source}
6	P1 D4 in	signal	p1_d4	from port 1 pin 7 ^{single source}
7	CPU D4	bus	dbus	^{single source}
8	GND	gnd	gnd	^{single source}
9	CPU D1	bus	dbus	output, driven from the +5V input on pin 10 ^{single source}
10	+5V	rail	vcc	tied high as a buffer input ^{single source}
11	CPU D2	bus	dbus	output, driven from the +5V input on pin 12 ^{single source}
12	+5V	rail	vcc	tied high as a buffer input ^{single source}
13	CPU D1	bus	dbus	second D1 driver, gated by pin 1 ^{single source}
14	+5V	rail	vcc	tied high as a buffer input ^{single source}
15	/OE2	signal	oe2	second-bank enable: $4017 read strobe ^{single source}
16	+5V	rail	vcc	^{single source}

Controller port 2 buffer + PPU A13 inverter TC40H368P (Toshiba) / SN74HC368N NESN-CPU-01 dip-16^{single source}^{opentendo-pcb,console5-101}#

U8 ('CII'): port 2 buffer on one half, and the spare gate inverts PPU A13 into /A13 for cart pin 58

Same part as U7 but wired differently, and this is where the top loader does something quietly useful: the second bank of the buffer is permanently enabled (pins 10, 14, 15 grounded) and one gate is used to invert PPU A13 into /PPU-A13, which is what leaves on cart pin 58 for nametable mirroring logic.

So a dead U8 costs you controller port 2 and breaks cart mirroring, which will look like a graphics fault, not a controller fault. Worth knowing before you chase the wrong subsystem.

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Interactive diagram needs JavaScript. The full pinout is in the table below.

Pin	Signal	Cat	Net	Note
1	/OE2	signal	oe2	buffer enable: $4017 read strobe from CPU pin 35 ^{single source}
2	P2 D0 in	signal	p2_d0	from port 2 pin 4 ^{single source}
3	CPU D0	bus	dbus	^{single source}
4	P2 D3 in	signal	p2_d3	from port 2 pin 6 ^{single source}
5	CPU D3	bus	dbus	^{single source}
6	P2 D4 in	signal	p2_d4	from port 2 pin 7 ^{single source}
7	CPU D4	bus	dbus	^{single source}
8	GND	gnd	gnd	^{single source}
9	unused	nc		unrouted ^{single source}
10	GND	gnd	gnd	^{single source}
11	/PPU-A13	signal	ppu_a13n	inverter output → cart pin 58 ^{single source}
12	PPU A13	bus	ppu_abus	inverter input, from PPU pin 25 ^{single source}
13	unused	nc		unrouted ^{single source}
14	GND	gnd	gnd	^{single source}
15	GND	gnd	gnd	second-bank enable tied low: the A13 inverter is always on ^{single source}
16	+5V	rail	vcc	^{single source}

Cartridge connector (72-pin, soldered) P1: 2.50 mm pitch, 68 contacts populated of 72 positions NESN-CPU-01 · NESP-101 edge-72^✓^{nesdev-cart,consolemods-pin,opentendo-pcb,console5-101,nesdev-exp}#

soldered through-hole and non-ZIF, unlike the front loader's socketed ZIF: different, better, still serviceable, never wear-proof

This connector is the reason people buy top loaders, so it is worth being precise about what it actually is. It is a soldered, through-hole, non-ZIF connector: game-tech describes it as “more like an ISA slot connector on a computer motherboard”, and the solder tails are visible entering the PCB in the component-side board photos. There is no spring cage to fatigue, which is the front loader’s signature failure. What it does still do is trap debris, corrode, and occasionally bend a pin, and because it is soldered rather than socketed it is a desolder job to replace, not a lift-and-swap. Write it up as different and better, not as wear-proof.

Pitch is 2.50 mm, not 2.54 mm. Four independent lines agree: NESdev says so outright, ConsoleMods says so, Ben Boldt measured it, and the OpenTendo footprint’s adjacent-pad delta is exactly 2.5 mm with each row spanning 87.5 mm. That gives you a free pre-solder test: put a ruler on any candidate connector, centre of pin 1 to centre of pin 36 must be 87.5 mm, not 88.9 mm. A true 2.54 mm part runs about 1.4 mm out of register across a row and cannot solder into this board at all. The generic “NES 72-pin connector” all over eBay is the front-loader NES-001 part.

Four contacts are physically absent. Pins 18, 19, 54, 55 (EXP2, EXP3, EXP6, EXP5) have no metal at all. Three sources agree: Console5, NESdev’s EXP-pins page, and the OpenTendo board file, whose P1 footprint simply has no pads at those four positions. Because EXP6 (pin 54) is the standard expansion-audio input, the top loader has no cart audio path in stock form.

A discrepancy I am not going to paper over. ConsoleMods’ connector pinout page claims “pins 16 through 19 and pins 52 through 55 are not physically present on the top loader”: eight missing contacts, not four. That contradicts its own table, which shows pin 51 as merely “Unused (NES-101)” rather than absent, and it contradicts NESdev’s EXP0/1/7/8 rows. It also contradicts the OpenTendo board file directly, where pads 16, 17, 20, 51, 52 and 53 all exist and are simply unrouted single-pad nets. I go with 18/19/54/55 (three sources against one), but if you are designing an adapter, dry-fit before you commit.

The four ex-CIC pins are repurposed, not merely dead. Design against this rather than distrusting it: pin 70 is +5 V, so a cart or adapter must tolerate it and must never drive it (pulling pin 70 low on a top loader shorts the 5 V rail). Pin 71 is a live PPU D4 line sharing a node with pin 69, so anything driven onto it fights the PPU bus. Pins 34 and 35 are safe no-connects. Confirmed three ways: the OpenTendo board netlist, NESdev’s raw wikitext, and ConsoleMods’ table. Fetch the NESdev page raw: a summarised fetch of the rendered page transposes the 34/70 and 35/71 pairing.

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Click a pin to see its signal, net, and sources.

Interactive diagram needs JavaScript. The full pinout is in the table below.

Pin	Signal	Cat	Net	Note
1	GND	gnd	gnd	^✓
2	CPU A11	bus	cpu_abus	^✓
3	CPU A10	bus	cpu_abus	^✓
4	CPU A9	bus	cpu_abus	^✓
5	CPU A8	bus	cpu_abus	^✓
6	CPU A7	bus	cpu_abus	^✓
7	CPU A6	bus	cpu_abus	^✓
8	CPU A5	bus	cpu_abus	^✓
9	CPU A4	bus	cpu_abus	^✓
10	CPU A3	bus	cpu_abus	^✓
11	CPU A2	bus	cpu_abus	^✓
12	CPU A1	bus	cpu_abus	^✓
13	CPU A0	bus	cpu_abus	^✓
14	CPU R/W	signal	rw	^✓
15	/IRQ	signal	irq	10K pull-up in RA1: safe to leave floating ^✓
16	EXP0	nc		contact present, unrouted on the top loader (no expansion port) ^{single source}
17	EXP1	nc		contact present, unrouted ^{single source}
18	EXP2	nc		NO CONTACT: no metal at this position on the NES-101 ^✓
19	EXP3	nc		NO CONTACT ^✓
20	EXP4	nc		contact present, unrouted ^{single source}
21	PPU /RD	signal	ppu_rd	^✓
22	CIRAM A10	signal	ciram_a10	the mirroring select: into VRAM U4 pin 19 ^✓
23	PPU A6	bus	ppu_abus	^✓
24	PPU A5	bus	ppu_abus	^✓
25	PPU A4	bus	ppu_abus	^✓
26	PPU A3	bus	ppu_abus	^✓
27	PPU A2	bus	ppu_abus	^✓
28	PPU A1	bus	ppu_abus	^✓
29	PPU A0	bus	ppu_abus	^✓
30	PPU D0	bus	ppu_dbus	^✓
31	PPU D1	bus	ppu_dbus	^✓
32	PPU D2	bus	ppu_dbus	^✓
33	PPU D3	bus	ppu_dbus	^✓
34	(CIC to cartridge on NES-001)	nc		FLOATS on the NES-101: safe no-connect ^✓
35	(CIC to motherboard on NES-001)	nc		FLOATS on the NES-101: safe no-connect ^✓
36	+5V	rail	vcc	^✓
37	SYSTEM CLK	signal	sysclk	meter this one: OpenTendo's board leaves the pad on its own net, see the card notes ^{single source}
38	M2	signal	m2	1.7897725 MHz: scope here to prove the CPU is running ^✓
39	CPU A12	bus	cpu_abus	^✓
40	CPU A13	bus	cpu_abus	^✓
41	CPU A14	bus	cpu_abus	^✓
42	CPU D7	bus	cpu_dbus	^✓
43	CPU D6	bus	cpu_dbus	^✓
44	CPU D5	bus	cpu_dbus	^✓
45	CPU D4	bus	cpu_dbus	^✓
46	CPU D3	bus	cpu_dbus	^✓
47	CPU D2	bus	cpu_dbus	^✓
48	CPU D1	bus	cpu_dbus	^✓
49	CPU D0	bus	cpu_dbus	^✓
50	/ROMSEL	signal	romsel	NAND of M2 and CPU A15, from U3 pin 9 ^✓
51	EXP9	nc		contact present, unrouted: this is the pin the expansion-audio mod uses ^✓
52	EXP8	nc		contact present, unrouted ^{single source}
53	EXP7	nc		contact present, unrouted ^{single source}
54	EXP6	nc		NO CONTACT, and EXP6 is the standard expansion-audio input, so stock cart audio is impossible here ^✓
55	EXP5	nc		NO CONTACT ^✓
56	PPU /WR	signal	ppu_wr	^✓
57	CIRAM /CE	signal	ciram_ce	→ VRAM U4 pin 18 ^✓
58	PPU /A13	signal	ppu_a13n	inverted A13, generated by U8 ^✓
59	PPU A7	bus	ppu_abus	^✓
60	PPU A8	bus	ppu_abus	^✓
61	PPU A9	bus	ppu_abus	^✓
62	PPU A11	bus	ppu_abus	out of sequence: 62/63 are A11/A10, not A10/A11 ^✓
63	PPU A10	bus	ppu_abus	out of sequence: see pin 62 ^✓
64	PPU A12	bus	ppu_abus	^✓
65	PPU A13	bus	ppu_abus	^✓
66	PPU D7	bus	ppu_dbus	^✓
67	PPU D6	bus	ppu_dbus	^✓
68	PPU D5	bus	ppu_dbus	^✓
69	PPU D4	bus	ppu_d4	same electrical node as pin 71 on this console ^✓
70	+5V (CIC +RST on NES-001)	rail	vcc	REPURPOSED to +5V: never drive this pin low on a top loader, it shorts the rail ^✓
71	PPU D4 (CIC CLK on NES-001)	bus	ppu_d4	REPURPOSED: live PPU data line sharing a node with pin 69 ^✓
72	GND	gnd	gnd	^✓

Controller port (7-pin, both ports) P4: single moulded 2-port assembly NESN-CPU-01 · NESP-101 header-7^✓^{nesdev-ctrl,consolemods-pin,opentendo-pcb}#

both ports are one moulded part on the top loader: you cannot replace just one

ConsoleMods’ controller table and the OpenTendo board pad numbering agree pin for pin, so this one is solid. The signals are identical between ports; only the CPU-side strobe differs ($4016 for port 1, $4017 for port 2).

The thing that trips people up is that the console’s CLK pin is not a dedicated clock generator: it is the read strobe off the CPU (pin 36 /INP0 for port 1, pin 35 /INP1 for port 2), which goes low during the read and returns high, and that rising edge is what clocks the controller’s 4021 shift register.

A discrepancy worth knowing. ConsoleMods labels pins 6 and 7 “D3 / D4 (port 2 only)”. On the top-loader board that is not what is wired: the OpenTendo netlist puts /4016-D3 and /4016-D4 on port 1 pins 6 and 7 as well, both with 10K pull-ups in RA1, both protected by the diode arrays, and both buffered into the CPU data bus by U7. Assume both ports carry D3/D4 here and meter before designing an accessory around ConsoleMods' wording.

Protection: each port gets a pair of 7-pin SIP diode arrays across its five active lines. DA1 (DAN601) and DA2 (UPA64H) on port 1, DA3/DA4 on port 2, clamping /OE, OUT0, D0, D3 and D4 between the rails. If a port is dead after somebody hot-plugged something, check the arrays and the buffer before you blame the port itself.

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Interactive diagram needs JavaScript. The full pinout is in the table below.

Pin	Signal	Cat	Net	Note
1	GND	gnd	gnd	brown on an OEM NES-001 lead ^✓
2	CLK	signal	clk	the /OE1 or /OE2 read strobe straight off the CPU; red lead ^✓
3	OUT0 (latch)	signal	out0	CPU pin 39, shared by BOTH ports; orange lead ^✓
4	D0 (data)	signal	d0	10K pull-up in RA1; yellow lead ^✓
5	+5V	rail	vcc	white lead ^✓
6	D3	signal	d3	wired on BOTH ports here, contra ConsoleMods; blue lead ^{single source}
7	D4	signal	d4	wired on BOTH ports here; purple lead ^{single source}

Power input jack ACPLUG1: 5.5 x 2.1 mm barrel NESN-CPU-01 · NESP-101 header-2^✓^{junkerhq-psu,gametech-power,opentendo-pcb,nesdev-t17506}#

barrel polarity is a DON'T CARE on NESN-CPU-01: the bridge rectifier is on the board, not in the brick

The OEM supply is an NES-002, a bare 9 V AC transformer, and the rectification happens inside the console: jack → T1 08RB01 coil → DB1 RC203 bridge → C13 1500 µF → power switch → 7805. Because the bridge is on the board, either barrel polarity works and so does DC. Junker HQ’s power-supply bible lists the NES-002 as “no orientation”, and game-tech says the same.

Two cautions. This don’t-care is specific to NESN-CPU-01: ConsoleMods says the JIO boards replace the bridge with two diode arrays, so do not generalise it to a PAL or service-replacement board without checking. And it does not run in reverse: never feed an NES-002 AC brick to a Famicom or a Sega console, which expect DC.

Design target if you are building a supply or a PD trigger dongle: 9-10 V, AC or DC, 850 mA or better. The floor is about 8.2-8.4 V DC in, because the bridge eats 1.1-1.4 V and the 7805 needs roughly 7 V, but design for 9 V, not for the floor, once C13’s ripple is counted. Actual console draw is around 400-600 mA at 5 V, and that figure is a conservative NES-001 number: the top loader has no CIC, no 74HCU04 and no expansion port.

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Pin	Signal	Cat	Net	Note
1	AC/DC in	rail	acin1	into T1, then the DB1 bridge: polarity irrelevant ^✓
2	AC/DC in	rail	acin2	the other leg; also polarity irrelevant ^✓

Address decoder (dual 2-to-4 demux) 74LS139-class: MB74LS139 (Fujitsu) / HD74LS139P (Hitachi) NESN-CPU-01 dip-16^{single source}^{opentendo-pcb,console5-101,nesdev-ppu}#

U3: makes /ROMSEL, the PPU /CS and the work-RAM /CE. Absorbed into the JIO chip on the redesigned boards

Both halves are in use and they are cascaded, which is the bit worth knowing. Decoder 2 takes M2 (pin 14) and CPU A15 (pin 13) with its enable grounded: its Y3 output is /ROMSEL out to cart pin 50, and its Y1 output loops back to pin 1 to enable decoder 1. Decoder 1 then takes CPU A13/A14 and produces the work-RAM /CE (pin 4) and the PPU /CS (pin 5). Pins 6, 7, 10 and 12 are unrouted.

NESdev describes this generically ("/CS is generated by the 74139 on the mainboard to map the PPU regs from $2000 to $3FFF") which corroborates the role; the per-pin wiring is OpenTendo only.

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Interactive diagram needs JavaScript. The full pinout is in the table below.

Pin	Signal	Cat	Net	Note
1	1G (enable)	signal	dec1_en	driven from pin 11: decoder 2's Y1 ^{single source}
2	CPU A13	bus	abus	1A ^{single source}
3	CPU A14	bus	abus	1B ^{single source}
4	/WRAM-CE	signal	wram_ce	1Y0 → U1 pin 18 ^{single source}
5	/PPU-CE	signal	ppu_ce	1Y1 → PPU pin 13 ^{single source}
6	1Y2	nc		unrouted ^{single source}
7	1Y3	nc		unrouted ^{single source}
8	GND	gnd	gnd	^{single source}
9	/ROMSEL	signal	romsel	2Y3 → cart pin 50 ^{single source}
10	2Y2	nc		unrouted ^{single source}
11	2Y1	signal	dec1_en	same node as pin 1: this is the cascade ^{single source}
12	2Y0	nc		unrouted ^{single source}
13	CPU A15	bus	abus	2B ^{single source}
14	M2	signal	m2	2A ^{single source}
15	2G (enable)	gnd	gnd	grounded: decoder 2 always enabled ^{single source}
16	+5V	rail	vcc	^{single source}

PPU address latch (octal transparent latch) 74LS373-class: MB74LS373 (Fujitsu) / HD74LS373P (Hitachi) NESN-CPU-01 · NESP-101 dip-20^{single source}^{opentendo-pcb,console5-101}#

U2: demultiplexes the PPU's AD0-AD7 into PPU A0-A7. Stays discrete even on the JIO boards

Nintendo second-sourced this position: Console5 lists a Hitachi HD74LS373P, the photographed OEM board carries a Fujitsu MB74LS373 marked MALAYSIA 9203 F14, and the silkscreen is just a generic 74LS373. Do not treat the HD prefix as an authenticity check. OpenTendo respecs it to a 74HC373, which is pin-compatible but not identical: the OEM part is bipolar LS.

Pin functions below are the standard 74x373 arrangement, read against the OpenTendo board nets: the D inputs sit on the PPU’s multiplexed AD bus and the Q outputs feed PPU A0-A7 out to the cart connector and the VRAM. Pin 1 (/OE) is hard-grounded, so the latch is always driving; pin 11 (LE) is the PPU’s ALE.

0° 1×

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Pin	Signal	Cat	Net	Note
1	/OE	gnd	gnd	grounded: outputs always enabled ^{single source}
2	PPU A7	bus	ppu_abus	1Q, latched output ^{single source}
3	PPU AD7	bus	ppu_adbus	1D, from PPU pin 31 ^{single source}
4	PPU AD6	bus	ppu_adbus	2D ^{single source}
5	PPU A6	bus	ppu_abus	2Q ^{single source}
6	PPU A5	bus	ppu_abus	3Q ^{single source}
7	PPU AD5	bus	ppu_adbus	3D ^{single source}
8	PPU AD4	bus	ppu_adbus	4D ^{single source}
9	PPU A4	bus	ppu_abus	4Q ^{single source}
10	GND	gnd	gnd	^{single source}
11	ALE (LE)	signal	ale	latch enable, from PPU pin 39 ^{single source}
12	PPU A3	bus	ppu_abus	5Q ^{single source}
13	PPU AD3	bus	ppu_adbus	5D ^{single source}
14	PPU AD2	bus	ppu_adbus	6D ^{single source}
15	PPU A2	bus	ppu_abus	6Q ^{single source}
16	PPU A1	bus	ppu_abus	7Q ^{single source}
17	PPU AD1	bus	ppu_adbus	7D ^{single source}
18	PPU AD0	bus	ppu_adbus	8D ^{single source}
19	PPU A0	bus	ppu_abus	8Q ^{single source}
20	+5V	rail	vcc	^{single source}

Video output amplifier (PNP) 2SA937 (Rohm), TO-92 NESN-CPU-01 header-3^✓^{nesdev-ppu,opentendo-pcb,rohm-2sa937}#

Q1: sits directly on PPU pin 21. This single emitter-follower IS the whole video chain

Lead order E-C-B comes from NESdev’s PPU-pinout page (which draws the 2SA937 next to its 2N3906 substitute precisely because the pinouts differ), and the OpenTendo board topology independently agrees: the base takes PPU pin 21 VOUT, the emitter goes to the R1 510R pull-up to +5 V and out through R2 430R, and the collector is grounded.

From the emitter the signal runs R2 430R into the R3 150R divider, through the FC2 ferrite, onto the /VIDEO net and into RF-modulator connector P6 pin 2. There is no composite buffer and no AV jack on this board: that is the entire path.

Two field notes. NESdev’s composite-mod circuit reuses this exact transistor rather than adding one, so if you are doing an AV mod, keep it. And game-tech has seen factory-repaired NES-101s where Nintendo replaced both Q1 and Q2, which makes these two the known-marginal discretes on the board.

Package caution: OpenTendo footprints Q1 (and Q2) as TO-126 while the Rohm datasheet says TO-92. That is a recreation artifact (a TO-92 still fits a 2.54 mm inline 3-pad pattern), not an OEM package fact.

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Pin	Signal	Cat	Net	Note
1	E (emitter)	signal	vid_e	R1 510R to +5V, R2 430R out to the video divider ^✓
2	C (collector)	gnd	gnd	grounded ^✓
3	B (base)	signal	vout	PPU pin 21 VOUT lands here ^✓

Master-clock oscillator transistor (NPN) 2SC2021 NESN-CPU-01 header-3^{single source}^{opentendo-pcb,opentendo-sch}#

Q2 is the 21.47727 MHz Colpitts oscillator: NOT an audio amp, whatever you have read

Correcting a mislabel that is easy to inherit: Q2 is commonly written up as an audio amplifier, and it is not. There is no audio transistor on this board at all: the stock audio path is a passive resistor mix. Q2 forms a Colpitts oscillator with X1 (21.47727 MHz), the TC1 30 pF trimmer, C7/C9, R8 150K collector-to-base bias, R9 1.2K collector load and R10 150R emitter degeneration. Its output leaves through C10 onto the SYS-CLK net, feeding CPU pin 29 and PPU pin 18. I traced that pad-to-net in the OpenTendo routed board file.

Diagnostic consequence: a dead Q2 gives you a perfect +5 V rail and a completely dead console. On a no-boot top loader, scope the clock before you touch anything else.

Lead order below is OpenTendo’s schematic symbol numbering (1=E, 2=C, 3=B), not necessarily the 2SC2021’s physical lead order: check the package before you assume. The passive values around it come from OpenTendo’s schematic and BOM, which are one project, so they are single-source; the topology and the part number are corroborated elsewhere.

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Pin	Signal	Cat	Net	Note
1	E (emitter)	signal	osc_e	R10 150R to ground, bypassed by C8 10nF ^{single source}
2	C (collector)	signal	osc_c	R9 1.2K to +5V; X1, TC1 and R8 all land here; C10 takes the output out as SYS-CLK ^{single source}
3	B (base)	signal	osc_b	C7 330pF to ground, R8 150K back to the collector ^{single source}

Pull-up resistor array (12 x 10K) RA1: 12-pin SIP (sub: Bourns 4612X-101-103LF) NESN-CPU-01 header-12^{single source}^{opentendo-pcb,opentendo-sch}#

one part holds up every controller line plus /IRQ, /NMI and PPU A13: a cracked SIP explains a lot of weirdness at once

Common-terminal SIP: pin 1 is the +5 V common and every other pin is a 10K pull-up to it. Worth knowing as a unit, because a single cracked or cold-jointed array can produce a symptom set that looks like several unrelated faults (floating controller data lines, spurious interrupts, and PPU A13 misbehaving), all at once.

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Pin	Signal	Cat	Net	Note
1	+5V common	rail	vcc	^{single source}
2	/OE2 pull-up	signal	oe2	port 2 CLK / $4017 strobe ^{single source}
3	$4017 D0 pull-up	signal	p2_d0	port 2 data ^{single source}
4	$4017 D3 pull-up	signal	p2_d3	^{single source}
5	$4017 D4 pull-up	signal	p2_d4	^{single source}
6	/OE1 pull-up	signal	oe1	port 1 CLK / $4016 strobe ^{single source}
7	$4016 D0 pull-up	signal	p1_d0	port 1 data ^{single source}
8	$4016 D3 pull-up	signal	p1_d3	^{single source}
9	$4016 D4 pull-up	signal	p1_d4	^{single source}
10	PPU A13 pull-up	signal	ppu_a13	^{single source}
11	/IRQ pull-up	signal	irq	this is why a cart can leave cart pin 15 floating ^{single source}
12	/NMI pull-up	signal	nmi	the PPU's /INT is open-drain and needs it ^{single source}

+5V linear regulator 7805 (OpenTendo specs ST L7805CV), TO-220 with heat sink NESN-CPU-01 · NESP-101 header-3^✓^{st-l78xx,opentendo-pcb,console5-101}#

U9 on NESN-CPU-01; renumbered U7 on the JIO/AV boards (fewer logic ICs)

Lead order is straight out of the ST L78xx datasheet and matches the board: IN, GND, OUT. Order on the schematic is DB1 (+) → C13 → the P2 power switch → 7805 IN → the +5 V rail, with C14 1µF on the output.

Two things worth carrying to the bench. First, the sources disagree about how much of a failure item this is: game-tech’s frequency data points at C13, not the regulator. Second, and this is the useful one, NESdev t=17501 shows the correct way to test it: a bad 7805 here reads fine out of circuit and unloaded, and only droops (~3.6 V measured) once it is carrying the console. Test it in circuit, or bench-load it at ~200 mA.

Before you condemn a regulator, rule out a downstream short: a healthy NES-001 reads about 255 Ω from +5 V to GND.

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Pin	Signal	Cat	Net	Note
1	IN	rail	vraw	unregulated DC from C13 via the power switch: roughly 11-13 V on a 9 VAC brick ^✓
2	GND	gnd	gnd	also the tab ^✓
3	OUT	rail	vcc	+5V rail, C14 1µF across it ^✓

RF modulator connector P6: 4-position NESN-CPU-01 · NESP-101 header-4^{single source}^{opentendo-pcb,console5-101}#

only four nets leave the board here: +5V, video, audio, ground. This is where every AV mod taps in

Small connector, disproportionately useful. Because there is no composite jack on a stock top loader, P6 is the boundary between the board and the RF can, and both the video and the audio you want for an AV mod are sitting on it in finished form.

Pin 2 carries /VIDEO: the output of the Q1 emitter follower after the R2/R3 divider and the FC2 ferrite. Pin 3 carries /AUDIO: the passive resistor mix off 2A03 pins 1 and 2, AC-coupled through C3 and the FC1 39 µH coil, with C5 10 nF shunting to ground. Console5’s audio mod tells you to tap “the leg of either R6 or R7” instead, which is the same node one component upstream.

The expansion-audio mod also lands here: the community move is a resistor from cart pin 51 (EXP9) to the audio pin on this connector, which is the one physically closest to pin 51.

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Pin	Signal	Cat	Net	Note
1	+5V	rail	vcc	powers the modulator ^{single source}
2	/VIDEO	signal	video	composite from Q1 via R2/R3 and the FC2 ferrite ^{single source}
3	/AUDIO	signal	audio	passive R6/R7 mix off 2A03 pins 1/2, via C3 and FC1 ^{single source}
4	GND	gnd	gnd	three ground pads on this position ^{single source}

CPU + APU (2A03) RP2A03G / RP2A03H (Ricoh, NTSC) NESN-CPU-01 dip-40^✓^{console5-2a03,opentendo-pcb,console5-101}#

U6. Unobtainium: no OEM stock since ~1999-2002; the only substitute is a donor pull or a UA6527 clone

Pin functions come from the Console5 Famicom 2A03 schematic sheet and are independently confirmed pin-for-pin by the OpenTendo NESN-CPU-01 board netlist, which names every pad’s net. The two sources agree on all 40 pins, including the easy-to-transpose OUT0/OUT1 pair (39/38).

Two things about this chip on THIS board that catch people out. Pin 29 is a clock input: the 2A03 has no gate oscillator of its own here, it is fed from the discrete Q2/X1 Colpitts, so a dead Q2 leaves a perfect +5 V rail and a completely dead console. And pins 37/38 (OUT2/OUT1) are unrouted single-pad nets on the top loader: with no bottom expansion port there is nothing for them to drive.

If you are pulling this chip, socket it. OpenTendo specs an On Shore ED40DT stamped dual-wipe DIP-40; for silicon this irreplaceable I would rather pay up for a machined-pin socket.

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Pin	Signal	Cat	Net	Note
1	/SOUND-1 (AUXA)	signal	snd1	audio out 1: R4 160R pulldown, mixes through R6 200R ^✓
2	/SOUND-2 (AUXB)	signal	snd2	audio out 2: R5 160R pulldown, mixes through R7 100R ^✓
3	/RST	signal	rst	reset switch P3 + C11 0.47µF debounce land here and nowhere else ^✓
4	A0	bus	abus	^✓
5	A1	bus	abus	^✓
6	A2	bus	abus	^✓
7	A3	bus	abus	^✓
8	A4	bus	abus	^✓
9	A5	bus	abus	^✓
10	A6	bus	abus	^✓
11	A7	bus	abus	^✓
12	A8	bus	abus	^✓
13	A9	bus	abus	^✓
14	A10	bus	abus	^✓
15	A11	bus	abus	^✓
16	A12	bus	abus	^✓
17	A13	bus	abus	also feeds U3 pin 2 (decoder 1A) ^✓
18	A14	bus	abus	also feeds U3 pin 3 (decoder 1B) ^✓
19	A15	bus	abus	not on the cart connector: U3 turns it into /ROMSEL ^✓
20	GND	gnd	gnd	^✓
21	D7	bus	dbus	^✓
22	D6	bus	dbus	^✓
23	D5	bus	dbus	^✓
24	D4	bus	dbus	^✓
25	D3	bus	dbus	^✓
26	D2	bus	dbus	^✓
27	D1	bus	dbus	^✓
28	D0	bus	dbus	^✓
29	CLK in (X IN)	signal	sysclk	21.47727 MHz from Q2/X1 via C10: shares a node with PPU pin 18 ^✓
30	X OUT	signal	gnd	internal-oscillator output, unused here: the OpenTendo board ties it to ground ^{single source}
31	M2 (φ2)	signal	m2	1.7897725 MHz bus strobe → cart pin 38; scope this to prove the CPU is running ^✓
32	/IRQ	signal	irq	10K pull-up in RA1; cart pin 15 ^✓
33	/NMI	signal	nmi	from PPU pin 19 /INT; 10K pull-up in RA1 ^✓
34	R/W	signal	rw	also drives both SRAMs' /WE and cart pin 14 ^✓
35	/INP1 (/OE2)	signal	oe2	$4017 read strobe: this IS the port-2 CLK line ^✓
36	/INP0 (/OE1)	signal	oe1	$4016 read strobe: this IS the port-1 CLK line ^✓
37	OUT2	nc		unrouted on NESN-CPU-01: no expansion port to drive ^{single source}
38	OUT1	nc		unrouted on NESN-CPU-01 ^{single source}
39	OUT0	signal	out0	controller latch: goes to BOTH ports' pin 3 ^✓
40	+5V	rail	vcc	^✓

CPU + APU (PAL) RP2A07 NESP-101 dip-40^{single source}^{nesdev-cpupal,consolemods-models}#

PAL counterpart of the 2A03: NESdev's CPU pinout page annotates this same 40-pin map for the 2A07 by name, so the equivalence is sourced rather than assumed

I previously left this stubbed rather than copy the 2A03 table across on a hunch. Going back to the source settles it: NESdev’s CPU pinout page carries ONE 40-pin diagram and then describes three of its pins specifically for the PAL part: pin 29 CLK (“divided by 12 (NTSC 2A03) or 16 (PAL 2A07)”), pin 30 TST (“on the RP2A07 … pulling pin 30 high instead causes the CPU to stop execution”), and pin 31 M2 (“in the PAL 2A07, M2 has a duty cycle of 19/32”). A page cannot annotate pins 29, 30 and 31 of a diagram for a part unless the diagram applies to that part. So the table below is published on that basis, and the equivalence is the source’s claim, not mine.

What is still missing, and why this stays single-source rather than verified: there is no board-level netlist for the NESN-CPU-JIO-02. The OpenTendo project only covers the NTSC NESN-CPU-01, and no OEM PAL schematic is public. So the CHIP pinout is sourced; how a particular PAL top loader routes it is not. If you are chasing a fault on a JIO-02, buzz the pin to its destination rather than trusting a net name.

The three PAL differences that actually matter at the bench: the master clock is 26.6017 MHz not 21.47727 MHz, the internal divider is 16 not 12 (so the CPU runs near 1.66 MHz rather than 1.79 MHz), and M2 on pin 31 has a 19/32 duty cycle instead of the NTSC 5/8. If you are comparing scope traces against an NTSC console, expect all three to differ and do not treat that as a fault.

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Pin	Signal	Cat	Net	Note
1	AD1	signal	snd1	audio out: both pulse channels ^{single source}
2	AD2	signal	snd2	audio out: triangle, noise, DPCM. The one pin that stays driven while /RST is held low ^{single source}
3	/RST	signal	rst	low holds the CPU in reset and floats every other pin; execution starts 6 M2 clocks after release ^{single source}
4	A0	bus	abus	^{single source}
5	A1	bus	abus	^{single source}
6	A2	bus	abus	^{single source}
7	A3	bus	abus	^{single source}
8	A4	bus	abus	^{single source}
9	A5	bus	abus	^{single source}
10	A6	bus	abus	^{single source}
11	A7	bus	abus	^{single source}
12	A8	bus	abus	^{single source}
13	A9	bus	abus	^{single source}
14	A10	bus	abus	^{single source}
15	A11	bus	abus	^{single source}
16	A12	bus	abus	^{single source}
17	A13	bus	abus	^{single source}
18	A14	bus	abus	^{single source}
19	A15	bus	abus	never reaches the cart edge: the board's decoder folds it into /ROMSEL ^{single source}
20	GND	gnd	gnd	^{single source}
21	D7	bus	dbus	the data bus runs D7 down to D0 across pins 21-28, backwards from the address block ^{single source}
22	D6	bus	dbus	^{single source}
23	D5	bus	dbus	^{single source}
24	D4	bus	dbus	^{single source}
25	D3	bus	dbus	^{single source}
26	D2	bus	dbus	^{single source}
27	D1	bus	dbus	^{single source}
28	D0	bus	dbus	^{single source}
29	CLK	signal	sysclk	PAL master clock in, 26.6017 MHz: divided by 16 internally on the 2A07 (12 on an NTSC 2A03), so the core runs near 1.66 MHz ^{single source}
30	TST	signal	gnd	grounded in the console. On the 2A07 specifically, pulling this high does NOT enable test registers the way it does on a 2A03G: it halts the core by deasserting the internal 6502 /RDY ^{single source}
31	M2	signal	m2	bus-ready strobe; on the 2A07 the duty cycle is 19/32 (357ns high in a 601ns period), not the NTSC 5/8. Scope this to prove the CPU is running ^{single source}
32	/IRQ	signal	irq	cart pulls low to interrupt ^{single source}
33	/NMI	signal	nmi	from the PPU's open-drain /INT: this is vblank ^{single source}
34	R/W	signal	rw	high = read, low = write; stays valid for the whole cycle ^{single source}
35	/OE2	signal	oe2	controller port 2 output enable ($4017 read strobe) ^{single source}
36	/OE1	signal	oe1	controller port 1 output enable ($4016 read strobe) ^{single source}
37	OUT2	signal	out2	$4016 write bit 2: expansion-port line, with nothing to drive on a top loader ^{single source}
38	OUT1	signal	out1	$4016 write bit 1: same ^{single source}
39	OUT0	signal	out0	$4016 write bit 0: the strobe that latches both controllers ^{single source}
40	+5V	rail	vcc	5.0 V logic rail ^{single source}

PPU (2C02) RP2C02G-0 / RP2C02H-0 (Ricoh, NTSC composite) NESN-CPU-01 dip-40^✓^{nesdev-ppu,opentendo-pcb,console5-101}#

U5. Pin 21 VOUT is the entire video source on this console: one PNP and it is in the RF can

NESdev’s composite-PPU pinout and the OpenTendo NESN-CPU-01 board netlist agree on all 40 pins, and they corroborate each other on two details that matter: EXT0-EXT3 (pins 14-17) are all tied to ground here, exactly as NESdev says they normally are, and pin 22 /RST is tied to +5 V.

That /RST tie is worth dwelling on. My own working notes for this console say the reset switch reaches CPU pin 3 and PPU pin 22: the routed OpenTendo board does not support that. On the board file the /RST net has exactly three members (P3, C11, CPU pin 3) and PPU pin 22 sits on /VCC. If that is right, the top loader behaves like a Famicom: pressing reset restarts the CPU but does not clear the screen. I have not put a meter on pin 22 to settle it, so treat both readings as provisional and check the pin before you design anything around it.

A dead PPU and a dead CPU are the same problem commercially: neither is made any more. Clone UA6528 PPUs exist and drop in, but every clone PPU has unreadable OAMDATA and palette RAM, which breaks flashcart savestate restore.

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Pin	Signal	Cat	Net	Note
1	R/W	signal	rw	from CPU pin 34 ^✓
2	CPU D0	bus	cpu_dbus	^✓
3	CPU D1	bus	cpu_dbus	^✓
4	CPU D2	bus	cpu_dbus	^✓
5	CPU D3	bus	cpu_dbus	^✓
6	CPU D4	bus	cpu_dbus	^✓
7	CPU D5	bus	cpu_dbus	^✓
8	CPU D6	bus	cpu_dbus	^✓
9	CPU D7	bus	cpu_dbus	^✓
10	CPU A2	bus	cpu_abus	register select ^✓
11	CPU A1	bus	cpu_abus	register select ^✓
12	CPU A0	bus	cpu_abus	register select ^✓
13	/CS (/DBE)	signal	ppu_ce	from U3 74LS139 pin 5: maps the regs at $2000-$3FFF ^✓
14	EXT0	gnd	gnd	grounded on this board ^✓
15	EXT1	gnd	gnd	grounded on this board ^✓
16	EXT2	gnd	gnd	grounded on this board ^✓
17	EXT3	gnd	gnd	grounded on this board ^✓
18	CLK	signal	sysclk	21.47727 MHz: same node as CPU pin 29 ^✓
19	/INT	signal	nmi	open-drain → CPU pin 33 /NMI, 10K pull-up in RA1 ^✓
20	GND	gnd	gnd	^✓
21	VOUT	signal	vout	shifted analog composite: straight into Q1's base, no buffer ^✓
22	/RST	rail	vcc	tied to +5V on NESN-CPU-01 per the routed board file: see the card notes ^{single source}
23	/WR	signal	ppu_wr	→ VRAM U4 pin 21, cart pin 56 ^✓
24	/RD	signal	ppu_rd	→ VRAM U4 pin 20, cart pin 21 ^✓
25	PPU A13	bus	ppu_abus	U8 inverts it into /A13 for cart pin 58 ^✓
26	PPU A12	bus	ppu_abus	^✓
27	PPU A11	bus	ppu_abus	^✓
28	PPU A10	bus	ppu_abus	^✓
29	PPU A9	bus	ppu_abus	^✓
30	PPU A8	bus	ppu_abus	^✓
31	PPU AD7	bus	ppu_adbus	multiplexed address/data: U2 latches the low byte ^✓
32	PPU AD6	bus	ppu_adbus	^✓
33	PPU AD5	bus	ppu_adbus	^✓
34	PPU AD4	bus	ppu_adbus	^✓
35	PPU AD3	bus	ppu_adbus	^✓
36	PPU AD2	bus	ppu_adbus	^✓
37	PPU AD1	bus	ppu_adbus	^✓
38	PPU AD0	bus	ppu_adbus	^✓
39	ALE	signal	ale	→ U2 74LS373 pin 11 (latch enable) ^✓
40	+5V	rail	vcc	^✓

PPU (PAL) RP2C07 NESP-101 dip-40^{single source}^{nesdev-ppupal,consolemods-models}#

PAL counterpart of the 2C02: NESdev heads this exact diagram 'Composite PPUs (2C02, 2C07)', so the 2C07 is named by the source, not inferred

This one is cleaner than the 2A07. NESdev’s PPU pinout page puts a single diagram under the heading “Composite PPUs (2C02, 2C07) are the standard PPU in consumer consoles”: the 2C07 is named as one of the two parts the diagram covers. The CLK description on the same page then gives the PAL side of pin 18 explicitly: 26.6017 MHz, divided by 5 for the pixel and memory clocks where NTSC divides by 4. So I am publishing the table with the source’s own equivalence claim behind it.

Still single-source, for the same reason as the 2A07: there is no board netlist for the NESN-CPU-JIO-02 and no public OEM PAL schematic, so the chip pinout is sourced but the board routing is not. Buzz before you cut.

The practical PAL differences are all downstream of pin 18 and pin 21: a slower pixel clock, 312 lines instead of 262, and a different colour subcarrier. Pin 21 is still the composite output and is still the split point I use: good video at pin 21 with nothing at the jack puts the fault in the output transistor or the modulator, not the PPU.

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Pin	Signal	Cat	Net	Note
1	R/W	signal	rw	from the CPU ^{single source}
2	CPU D0	bus	dbus	^{single source}
3	CPU D1	bus	dbus	^{single source}
4	CPU D2	bus	dbus	^{single source}
5	CPU D3	bus	dbus	^{single source}
6	CPU D4	bus	dbus	^{single source}
7	CPU D5	bus	dbus	^{single source}
8	CPU D6	bus	dbus	^{single source}
9	CPU D7	bus	dbus	^{single source}
10	CPU A2	bus	abus	register select ^{single source}
11	CPU A1	bus	abus	register select ^{single source}
12	CPU A0	bus	abus	register select ^{single source}
13	/CS	signal	cs	maps the PPU registers at $2000-$3FFF; also written /DBE. On the JIO-02 the custom PIO does this decode, not a 74139 ^{single source}
14	EXT0	signal	ext	grounded on a console ^{single source}
15	EXT1	signal	ext	grounded on a console ^{single source}
16	EXT2	signal	ext	grounded on a console ^{single source}
17	EXT3	signal	ext	grounded on a console: grounding all four sets the backdrop to palette entry 0 ^{single source}
18	CLK	signal	sysclk	PAL master clock in, 26.6017 MHz: the 2C07 divides it by 5 for the pixel and memory clocks where an NTSC 2C02 divides by 4 ^{single source}
19	/INT	signal	nmi	open-drain vblank interrupt into CPU /NMI, needs its pull-up ^{single source}
20	GND	gnd	gnd	also the reference for the composite output on pin 21 ^{single source}
21	VOUT	signal	vout	composite video out: the split point between the PPU and everything downstream of it ^{single source}
22	/RST	signal	rst	clears the picture on reset ^{single source}
23	/WR	signal	ppu_wr	VRAM write; cart edge pin 56 ^{single source}
24	/RD	signal	ppu_rd	VRAM read; cart edge pin 21 ^{single source}
25	PPU A13	bus	ppu_abus	^{single source}
26	PPU A12	bus	ppu_abus	^{single source}
27	PPU A11	bus	ppu_abus	^{single source}
28	PPU A10	bus	ppu_abus	^{single source}
29	PPU A9	bus	ppu_abus	^{single source}
30	PPU A8	bus	ppu_abus	^{single source}
31	PPU AD7	bus	ppu_adbus	multiplexed address/data: the low byte is latched out of these eight by the 373 under ALE ^{single source}
32	PPU AD6	bus	ppu_adbus	^{single source}
33	PPU AD5	bus	ppu_adbus	^{single source}
34	PPU AD4	bus	ppu_adbus	^{single source}
35	PPU AD3	bus	ppu_adbus	^{single source}
36	PPU AD2	bus	ppu_adbus	^{single source}
37	PPU AD1	bus	ppu_adbus	^{single source}
38	PPU AD0	bus	ppu_adbus	^{single source}
39	ALE	signal	ale	address latch enable: goes high for one PPU cycle at the start of each VRAM access and drives the 373's latch enable ^{single source}
40	+5V	rail	vcc	5.0 V logic rail ^{single source}

Work / video SRAM (2K x 8) LH5216AD-10L (Sharp); 6116-class DIP-24 narrow NESN-CPU-01 · NESP-101 dip-24^{single source}^{opentendo-pcb,console5-101}#

two of these: U1 = CPU work RAM, U4 = PPU CIRAM. Same part, different bus

The pin table is read out of the OpenTendo routed board file, where every pad carries a named net, and it lines up exactly with the standard 6116 2Kx8 arrangement. I have not put an LH5216AD datasheet in the library, so it stays single-source, but the wiring is self-consistent, and the two board-specific details it reveals are the useful part: pin 20 (/OE) is tied straight to ground, and pin 21 (/WE) is driven directly off the CPU’s R/W line with no gating.

Nets shown are for U1 (work RAM, on the CPU bus). U4 is the identical part on the PPU bus: pins 1-8 are PPU A7-A0, pins 9-17 are PPU D0-D7, pin 18 is /VRAM-CE from cart pin 57, pin 19 is CIRAM A10 from cart pin 22, pin 20 is PPU /RD and pin 21 is PPU /WR.

Sourcing: OpenTendo names a Renesas 6116SA15TPG but carries no Digi-Key or Mouser SKU for it. It is EOL at the majors. Any 2Kx8 async SRAM in DIP-24, 300 mil, 150 ns or faster is functionally correct. Do not order a 600-mil DIP-24; it will not drop into the footprint.

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Pin	Signal	Cat	Net	Note
1	A7	bus	abus	^{single source}
2	A6	bus	abus	^{single source}
3	A5	bus	abus	^{single source}
4	A4	bus	abus	^{single source}
5	A3	bus	abus	^{single source}
6	A2	bus	abus	^{single source}
7	A1	bus	abus	^{single source}
8	A0	bus	abus	^{single source}
9	I/O0	bus	dbus	^{single source}
10	I/O1	bus	dbus	^{single source}
11	I/O2	bus	dbus	^{single source}
12	GND	gnd	gnd	^{single source}
13	I/O3	bus	dbus	^{single source}
14	I/O4	bus	dbus	^{single source}
15	I/O5	bus	dbus	^{single source}
16	I/O6	bus	dbus	^{single source}
17	I/O7	bus	dbus	^{single source}
18	/CE	signal	ce	U1: /WRAM-CE from U3 pin 4. U4: /VRAM-CE, shared with cart pin 57 ^{single source}
19	A10	bus	abus	U4: this is CIRAM A10 from cart pin 22. The mirroring select ^{single source}
20	/OE	gnd	gnd	U1: hard-grounded, always output-enabled. U4: driven by PPU /RD ^{single source}
21	/WE	signal	we	U1: straight off CPU R/W. U4: PPU /WR ^{single source}
22	A9	bus	abus	^{single source}
23	A8	bus	abus	^{single source}
24	+5V	rail	vcc	^{single source}

Master clock crystal 21.47727 MHz, HC-49U (sub: ECS-214-S-4X) NESN-CPU-01 header-2^✓^{opentendo-pcb,opentendo-sch,nesdev-ppu}#

NTSC master clock. Same value as the front loader. The PAL NESP-101 value is NOT sourced anywhere in my library

One crystal on the whole board. There is no second 4 MHz CIC oscillator, because there is no CIC. That absence is itself a useful structural check: if you are looking at an NES board with two crystals, it is not a top loader.

TC1, the 30 pF trimmer sitting in parallel with C9 across this crystal, trims the master clock and therefore the colorburst (master ÷ 6 = 3.579545 MHz). It is not a tint pot: it moves CPU, PPU and colorburst together, so a mis-adjusted or cracked TC1 shows up as colour problems rather than a dead console. Leave it alone unless a frequency counter says the clock is out of spec.

0° 1×

Click a pin to see its signal, net, and sources.

Interactive diagram needs JavaScript. The full pinout is in the table below.

Pin	Signal	Cat	Net	Note
1	XTAL	signal	osc_c	Q2 collector node, with TC1 and R8/R9 ^{single source}
2	XTAL	signal	osc_fb	C9 10pF feedback leg ^{single source}

Schematic facts

Master clock (NTSC): 21.47727 MHz (X1 + Q2 Colpitts oscillator; same value as the front loader)^✓^{opentendo-sch,nesdev-ppu}
notes
Colorburst is master ÷ 6 = 3.579545 MHz, and TC1 trims the master, so TC1 is a colour-symptom adjustment, not a dead-console one.
CPU bus strobe M2: 1.7897725 MHz (master ÷ 12) (CPU pin 31 → cart pin 38; scope here to prove the CPU is running)^✓^{opentendo-sch,nesdev-cart}
Master-clock oscillator is Q2, not an audio amp: 2SC2021 Colpitts with X1, TC1 30pF, C7/C9, R8 150K, R9 1.2K, R10 150R (traced pad-to-net in the routed board file: this corrects a common mislabel)^{single source}^{opentendo-pcb}
notes
There is no audio transistor anywhere on this board. If a write-up calls Q2 an audio amplifier, it is wrong.
Stock audio path: passive resistor mix: 2A03 pin 1 /SOUND-1 and pin 2 /SOUND-2 (R4/R5 160R pulldowns, mixed via R6 200R and R7 100R, coupled by C3 1µF through FC1 39µH to P6 pin 3)^✓^{opentendo-pcb,console5-101}
notes
C4 220pF sits at the mix node and C5 10nF shunts the audio net. Console5’s audio-mod instructions independently say to tap the leg of R6 or R7, or CPU pins 1 and 2 for pseudo-stereo: which is the same path from the other end.
Stock video path: PPU pin 21 VOUT → Q1 2SA937 → R1 510R / R2 430R / R3 150R → FC2 ferrite → P6 pin 2 (one emitter follower is the entire video chain: there is no composite buffer and no AV jack)^✓^{opentendo-pcb,nesdev-ppu}
+5V rail: 7805 linear, C14 1µF on the output (a healthy NES-001 reads ~255 Ω from +5V to GND: use that as your short-hunting baseline)^✓^{opentendo-sch,st-l78xx}
Raw rail after the bridge: roughly 11-13 V DC on a 9 VAC brick; ~7.6-8.9 V on a 9 V DC cube (C13 sits on this node and STAYS CHARGED with the console switched off)^✓^{opentendo-sch,gametech-power}
Power input spec: 9-10 V AC or DC, ≥850 mA, 5.5 x 2.1 mm barrel, polarity irrelevant (OEM is the NES-002, a bare 9 V AC transformer; the bridge is inside the console)^✓^{junkerhq-psu,gametech-power,nesdev-t17506}
notes
Minimum usable DC in is about 8.2-8.4 V once you subtract the 1.1-1.4 V bridge drop from the 7805’s ~7 V floor, but design for 9 V, not the floor. Console draw is ~400-600 mA at 5 V, and that number is a conservative NES-001 figure.
Lockout chip: NONE: the CIC footprint is not populated (no lockout IC in the schematic or BOM, zero CIC nets on the routed board, and only ONE crystal where the NES-001 needs two)^✓^{opentendo-pcb,console5-101,consolemods-region}
notes
Consequence: there is no 1 Hz reset generator, so the front loader’s blinking-power-LED reboot loop cannot happen here. A dirty or bent cart contact gives you a garbled screen, a black screen or a lock-up instead. Unlicensed and other-region carts often just run.
Cart contacts physically absent: pins 18, 19, 54, 55 (EXP2, EXP3, EXP6, EXP5): no metal at all (three sources agree; ConsoleMods' claim of eight missing contacts (16-19 and 52-55) contradicts its own table and the board file)^✓^{console5-101,nesdev-exp,opentendo-pcb}
notes
Because EXP6 = pin 54 is the standard expansion-audio input, the top loader has no cart audio path in stock form. EXP9 = pin 51 is present but unrouted, and is the community’s substitute.
Repurposed ex-CIC cart pins: 70 = +5V · 71 = PPU D4 (same node as 69) · 34 and 35 float (design adapters TO this remap: pulling pin 70 low shorts the 5V rail)^✓^{nesdev-cart,opentendo-pcb,consolemods-pin}
Cart connector pitch: 2.50 mm: pin 1 to pin 36 spans 87.5 mm (NOT 2.54 mm; a standard 0.1-inch part measures 88.9 mm and cannot solder in)^✓^{nesdev-cart,consolemods-pin,nesdev-t7449,opentendo-pcb}
Cart pin 37 (SYSTEM CLK): unresolved on this board: meter it (the OpenTendo schematic labels the cart pad SYSTEM-CLK while the CPU/PPU clock net is SYS-CLK, so the routed board leaves the pad on its own single-pad net)^{single source}^{opentendo-pcb,nesdev-cart}
notes
That looks like a net-label artifact in the recreation rather than an OEM board fact: the 72-pin standard puts the master clock on pin 37, and the usual dead-board procedure is to scope it there. But I have not confirmed continuity from Q2 to cart pin 37 on real hardware, so if you are relying on that measurement, buzz it out first.
Electrolytic count: five: C1, C3, C11, C13, C14 (everything else on the board is ceramic; this is a light recap)^✓^{console5-101,opentendo-sch,gametech-mods}
notes
Sources say the five-cap recap is really a one-cap repair: game-tech reports only two of the five have ever caused problems across dozens of units, with the power-circuit cap (C13) the one they have replaced 50-plus times. Repeating that as their finding, not mine.
Never power the board with an electrolytic out of circuit: sources say it cooked both the CPU and the PPU (one repair log, unproven mechanism, but the rule costs nothing and the CPU/PPU are the unobtainium parts)^{single source}^{nesdev-t17501}
notes
The NESdev t=17501 owner powered up mid-recap with at least one rail cap lifted (he thought C1, and was not sure) and afterwards both the RP2A03 and the RP2C02 had failed short. The proposed mechanism (7805 output oscillation from missing filtering) is explicitly a hypothesis, and it is shaky: C14 sits on the regulator’s OUT node independently, and the ST datasheet says no output capacitor is needed for stability. His own competing theory, a dying PPU that a fresh regulator could finally supply enough current to kill, was never ruled out. I follow the rule anyway.
Expansion-audio mod resistor: sources say 1.2k from cart pin 51 (EXP9) to the RF-connector audio pin (one NESdev poster's empirical value, arrived at by ear: not a spec)^{single source}^{nesdev-t7880,consolemods-expaudio}
notes
The 1.2k traces back to a single Bregalad post: he tried different values until 1.2k was the one that sounded balanced. Other modders landed elsewhere, and the value is destination-dependent: 47k plus a 1k pull-down is the standard figure going into an NESRGB, even on a top loader. Treat 1.2k as a starting point to tune by ear, not a number to trust. Note the naming trap: EXP9 is expansion pin 6 and EXP6 is expansion pin 9.
PAL (NESP-101) crystal value: NOT SOURCED: measure it (no source in my library states the NESP-101 X1 value; do not copy the front-loader PAL figure from memory)^bench^mem-bench

Reference confidence key

How to read the confidence tags and source citations on the data above.

Sources

console5-101: Console5 TechWiki: Nintendo NES-101 (wiki.console5.com/wiki/Nintendo_NES-101, oldid=7237)
console5-2a03: Console5 Famicom 2A03 CPU schematic sheet (console5-famicom-2a03-cpu.png): U6 2A03E pin-by-pin
console5-bu3270: Console5 TechWiki: BU3270S (wiki.console5.com/wiki/BU3270S, oldid=3440). Reproduces Jacques Gagnon's nes_pio_pinout.txt
console5-capmap: Console5 NES-101 cap map, © 2011/2015 Luke Sandel: board locations for C1/C3/C11/C13/C14 (designators only, no values)
consolemods-expaudio: ConsoleMods Wiki: NES expansion-audio mod (retrieved 2026-07-12)
consolemods-models: ConsoleMods Wiki: NES Model Differences (consolemods.org/wiki/NES:NES_Model_Differences, retrieved 2026-07-12)
consolemods-pin: ConsoleMods Wiki: NES Connector Pinouts (consolemods.org/wiki/NES:Connector_Pinouts, oldid=33417)
consolemods-region: ConsoleMods Wiki: NES Region Information (retrieved 2026-07-12)
gametech-intro: game-tech.us nes2-intro (retrieved 2026-07-13): non-ZIF connector, factory-repaired board population
gametech-mods: game-tech.us NES top-loader mods page (retrieved 2026-07-13): the cap-failure-frequency claims
gametech-power: game-tech.us NES-101 power research (retrieved 2026-07-13): bridge drop, PSU comparison, jailbar debunk
junkerhq-psu: Junker HQ 'The Console Power Supply Bible', NES rows: NES-002: AC 9V 1.3A, 5.5/2.1 mm plug, no orientation
mem-bench: My bench notes
nerdly: Nerdly Pleasures: 'Official Variations of the Nintendo 8-bit Hardware' and 'NES Hardware Explained' (retrieved 2026-07-12)
nesdev-cart: NESdev Wiki: Cartridge connector (nesdev.org/wiki/Cartridge_connector, oldid=23255, raw wikitext, retrieved 2026-07-13)
nesdev-cpupal: NESdev Wiki: CPU pinout (nesdev.org/wiki/CPU_pinout), raw wikitext retrieved 2026-07-27. One 40-pin diagram; the signal descriptions call out CLK (29), TST (30) and M2 (31) specifically for the PAL RP2A07
nesdev-ctrl: NESdev Wiki: Controller port pinout (nesdev.org/wiki/Controller_port_pinout, oldid=22054, retrieved 2026-07-12)
nesdev-exp: NESdev Wiki: EXP pins (nesdev.org/wiki/EXP_pins, retrieved 2026-07-12)
nesdev-ppu: NESdev Wiki: PPU pinout (nesdev.org/wiki/PPU_pinout, oldid=21822, retrieved 2026-07-12)
nesdev-ppupal: NESdev Wiki: PPU pinout, raw wikitext retrieved 2026-07-27. The composite-PPU diagram is headed 'Composite PPUs (2C02, 2C07) are the standard PPU in consumer consoles', and the CLK description gives the PAL clock and the PAL divisor
nesdev-t17501: NESdev forum t=17501: NES-101 dead-board / power / PPU troubleshooting thread
nesdev-t17506: NESdev forum t=17506: NES power adaptor spec thread (lidnariq on minimum DC input and current draw)
nesdev-t23781: NESdev forum t=23781: top loader with a corroded cart connector; Ben Boldt on 2.50 mm vs 2.54 mm pitch
nesdev-t7296: NESdev forum t=7296: questions regarding the NES power supply (bridge drop, 7805 floor)
nesdev-t7449: NESdev forum t=7449: sourcing a 72-pin connector for the top loader (tepples' 87.5 mm pin-1-to-pin-36 span test)
nesdev-t7880: NESdev forum t=7880: top-loader expansion audio via PowerPak (Bregalad's 1.2k value)
opentendo-pcb: OpenTendo-TopLoader v1.1 routed board file (opentendo-toploader-motherboard.kicad_pcb): pad-to-net netlist of the NESN-CPU-01 recreation, github.com/Redherring32/OpenTendo-TopLoader
opentendo-sch: OpenTendo-TopLoader v1.1 schematic + BOM (opentendo-toploader-motherboard.kicad_sch, opentendo-toploader-bom-v1.1.csv): same project, so NOT independent of opentendo-pcb
rohm-2sa937: Rohm 2SA937 PNP datasheet (via alldatasheet, retrieved 2026-07-13): TO-92 package, E/C/B lead order
st-l78xx: STMicroelectronics L78xx positive voltage regulator datasheet, DocID2143 Rev 26: TO-220 pin connections + stability notes

Confidence: verified two+ sources agree · single source one source / scan-derived, treat with care · bench my own measurement or practice.

Sources and further reading

These are the outside references I trust for the NES-101. I link them rather than copy them; go read the originals. Several are open-hardware or licensed works (OpenTendo under the TAPR Open Hardware License, the Console5 AV-mod schematic, the Wikimedia board photos under CC-BY-SA), and I link to those rather than reproduce the drawings or images.