NES Front-Loader (NES-001) Repair Reference

Dead or stuck buttons on one port, with the other port fine, is the pattern that sends me here. Nintendo’s port-fault chain is these buffers, the CPU, the DA1-DA4 diode arrays, and the RA1/RA2 resistor arrays, in that order.

Pin data is the Philips 74HC/HCT368 product specification, which is the lineage the PC74HC368P marking comes from, cross-checked against Nexperia’s current rev 5 sheet for the same part. The EDC schematic lists U7 and U8 as 74HC368 with power on 16 and ground on 8, which agrees.

Read the package as six inverting three-state buffers split into a group of four (enabled by pin 1) and a group of two (enabled by pin 15), which is the odd bit of the ‘368: it is not a clean 3+3 split. Both enables are active low. Note the outputs INVERT: the controller data arriving at an A pin comes out of the matching Y pin flipped, which is exactly what you want when the pad’s switches pull to ground.

Marking to expect on the board: OpenTendo draws U7 and U8 as “40H368”, which is the Nintendo house number. The EDC sheet calls the same positions 74HC368. Same part.

Console and cartridge carry the same die. Pin 4 decides which one it is: pulled to +5V it is the lock (the console), grounded it is the key (the cart). That is the whole basis of the pin-4 disable mod: lift pin 4 and the console’s CIC stops behaving as a lock, and the internal pulldown reads the floating pin as a key.

The handshake runs over cart edge pins 34 and 35 with both chips clocked from the shared 4 MHz oscillator on pin 6 (cart edge pin 71); the lock resets the cart’s key through its pin 10 and cart edge pin 70. When the handshake fails, the lock pulses /host reset (pin 9) at about 1 Hz: the famous blink. In practice that is nearly always a dirty or bent 72-pin connector, not a dead CIC.

Two cautions. First, Vcc is pin 16 and ground is pin 8, so this is not the pin-14/pin-7 layout your muscle memory expects from 74-series logic. Second, the CIC circuit is tangled up with the power LED and reset path, so a simple pin-4 cut can kill the LED; on a unit I care about I use the reversible two-wire method instead.

Pins 1, 2, 3, 4, 6, 9 and 10 are corroborated by the OpenTendo CPU-11 sheet and the EDC schematic. The remaining port pins come from the NESdev pinout alone.

Two fully independent buses cross this connector: the CPU bus (A0-A14, D0-D7, R/W, M2, /ROMSEL, /IRQ) and the PPU bus (A0-A13, D0-D7, /RD, /WR, /A13, plus CIRAM A10 and CIRAM /CE going back into the console). Power is +5V on pin 36 with ground on pins 1 and 72, and the lockout handshake lives on pins 34, 35, 70 and 71.

Two traps in the numbering. PPU A10 and A11 land on pins 63 and 62: out of order, deliberately. And the pitch is 2.50 mm, not 2.54 mm, so a generic 0.1-inch card-edge socket will not fit; do not scavenge one.

Nametable mirroring is decided in the cartridge, not the console: the cart drives CIRAM A10 (pin 22) from either PPU A10 or PPU A11 through solder jumpers, and enables the console’s own 2K nametable RAM through CIRAM /CE (pin 57).

There is no audio on this connector. The Famicom’s 60-pin edge loops cart audio through pins 45 and 46; the 72-pin NES edge has no equivalent, which is why expansion audio from a flashcart needs the resistor mod through the underside expansion port instead.

Before I do any electrical diagnosis on a misbehaving cart, I clean and re-tension this connector. Nintendo’s own service procedure starts there too.

Read this table as single-source and meter before you trust a number. The pin NUMBERS come from GameSX, which is the table the other wikis copy. The signal SET is beyond doubt (ground, +5V, the strobe, the clock, the serial data line, plus two auxiliary data lines) and NESdev’s own drawing shows the same seven signals, but NESdev does not number its drawing and its physical ordering of the clock, strobe and data column does not match GameSX’s numbering. Until I have metered a port myself I am not calling this verified.

How the interface works: the controller holds eight buttons on a 4021 parallel-in serial-out shift register, pulled high through about 45k and grounded by the switches. CPU OUT0 (CPU pin 39) strobes the latch, then each read at $4016 or $4017 clocks one bit out. /OE1 (CPU pin 36) and /OE2 (CPU pin 35) enable port 1 and port 2 respectively, and the 74HC368 buffers at U7/U8 put the returned data on the CPU bus.

Dead port with a known-good pad: the fault chain Nintendo publishes is the 368 buffers, the CPU, the DA1-DA4 diode arrays, then the RA1/RA2 pull-up resistor arrays.

The single most useful fact about this jack: it is unpolarised. The NES-002 is a bare transformer putting out about 9 VAC, and the bridge rectifier is inside the power module, so a DC supply of either polarity also runs the console. Roughly 9-10 V at 850 mA or better is the practical floor.

The reverse is emphatically not true. Do not put an NES-002 on a centre-negative DC-input console such as a Famicom or a Sega machine; the AC output will damage it.

Unloaded the jack reads high, around 9-10 VAC. That is normal and not a fault.

This is a 48-pin card edge on the underside, not a D-sub. It is commercially near-unused, which makes it a convenient tap: it carries composite video (pin 21), amplified audio (pin 22), the audio mixer input (pin 3), the unregulated adapter rail (pin 23), the 4 MHz CIC clock (pin 24), all ten EXP lines from the cartridge edge, the full CPU data bus, and the raw joypad data lines from both ports.

The expansion-audio mod uses exactly two of these: EXP6 on pin 9 into the audio mix input on pin 3, with ground on pin 2, optionally through a 1k resistor. That is the whole reason the mod exists, since the 72-pin cart edge carries no audio of its own.

Two cautions from the NESdev notes. /NMI on pin 4 is open-collector. And /IRQ on pin 14 should be used through a series 1k resistor rather than driven directly. Pins marked as available “only when nothing else is using that bit” are the joypad /D0, /D3 and /D4 lines: a Four Score, Zapper, Power Pad or Arkanoid controller in the front ports takes them.

Single-source: this pinout is NESdev’s. The three pins the audio mod uses (2, 3 and 9) are independently corroborated by the ConsoleMods mod guide.

This is not a connector you unplug. The module is soldered to the mainboard through five signal and power pins plus its ground tabs. Two things about it matter more than the pin table.

The isolation trick: inject a clean 5 V into the centre pin of this five-pin group, with ground, and the whole power and RF module is bypassed. If the console then plays, the fault is confined to the module. That single test saves a lot of blind desoldering on a dead deck.

The removal technique: pull the module’s top shield and desolder these five pins from the MODULE PCB, not from the NES mainboard. The mainboard traces to these pins are top-side only, and their vias dislodge easily. If you lift one you lose a signal on reassembly and will not know which.

The last two pins are now filled from the EDC power/AV/RF sheet, which numbers all five crossings between the module and the mainboard. Pins 4 and 5 are both the raw rectified rail, and the reason there are two of them is the front power switch: the module sends the rail out on pin 5, the mainboard runs it through the switch on P6, and it comes back on pin 4 to feed the 7805. There is no ground pin in this group at all: ground returns through the module’s solder tabs, which is exactly why an injection test needs its own ground lead.

That also gives you a fast switch test. With the console on, pin 5 and pin 4 should both sit at the raw rail. Rail on 5 and nothing on 4 is the power switch or its wiring, not the module.

Nintendo’s fault tables implicate the 74139 in lockups and blank screens, which makes sense: if the PPU never gets chip-selected, nothing draws.

Some NES-CPU-04 boards were built with a 74HC139 in this position instead of the LS part, and that does not change anything here: ON Semiconductor’s SN74LS139 sheet and TI’s CD74HC139 sheet give the same 16 pins in the same order. The EDC schematic draws U3 with the same numbering, and it also confirms how Nintendo wired it: CPU A13 into pin 2 and A14 into pin 3 on the enabled half, with the other half’s enable (pin 15) tied to ground so it runs permanently from A15 on pin 13.

The naming across datasheets is a mess for the same silicon: ON Semi calls the pins E / A0 / A1 / O0-O3, TI’s HC sheet calls them 1E / 1A0 / 1A1 / 1Y0-1Y3, and the EDC drawing uses C / A / B / Y0-Y3. I have listed them in the TI form with the enable spelled out, because that is the one that makes the active-low behaviour obvious. All outputs are active low, so on a live board only one output per enabled half should ever be low at once.

Unlike the SNES pad (Nintendo house parts, no substitute) the NES controller runs on an ordinary CD4021B. If the shift register is dead you buy a new one rather than hunting a donor.

Eight buttons on eight parallel inputs, shifted out of Q8 on pin 3. The button inputs are held high by a 45 kΩ × 8 resistor network and pulled to ground by the carbon contact pads. Some pads fit a 3.6 kΩ resistor on the OUT0 line and some do not: the drawing annotates it as “not present in all models”, so do not treat its absence as a fault.

Pin numbers are from a single drawing, hence single-source. Two things corroborate it: the button-to-pin map is internally consistent, and the three signal pins agree with the console-side controller-port card.

This is the substitution trap on this board. The HCU part has a single inverter stage, so with resistive feedback it settles into a stable linear region and works as the console’s audio amplifier. A buffered HC04, HCT04 or LS04 has three cascaded stages, far more open-loop gain and phase shift, and it oscillates or distorts instead. The DC bias still forms, so it looks right on a meter and sounds wrong.

Note that the OpenTendo schematic sheet labels this position 74LS04 while its own build BOM specifies SN74HCU04N. The BOM is the one that matches Console5 and the EDC schematic, and it is the one that describes a board that actually works. Check the chip in front of you before substituting.

The pin table is TI’s SN74HCU04 sheet, whose first feature line is literally “Unbuffered Outputs”: that is the part you have to order, and the U in the middle of the part number is the whole point. Anything without it has three cascaded stages and will not sit in a linear region. The EDC schematic lists U9 with power on 14 and ground on 7, matching, and it draws the audio amplifier explicitly as the gate on pins 11 and 10: input on 11 (5A), output on 10 (5Y), 47k from output back to input, 220pF across the feedback and another 220pF from the input to ground.

That means pin 11 and pin 10 are the two most useful probe points on this chip. On a healthy console both sit at roughly half the rail with audio riding on them. Both sitting hard at 0 V or 5 V means the gate has lost its bias (which is what a buffered substitute does), and the console goes silent with everything else working.

The remaining gates do inversion and clock shaping elsewhere on the board; the EDC sheet draws several of them over in the reset and lockout area. Do not assume every inverter symbol on that sheet is this chip: the CIC oscillator has its own. Numbering is the standard hex-inverter map: odd pins 1/3/5 and 9/11/13 are inputs, and each output sits directly opposite its input in the package order below.

Scrambled graphics on a game that is otherwise running is the classic symptom that points here, along with the video RAM and the PPU. Nintendo’s own service workbook names the 74373 in both the scrambled-video and one blank-screen-with-sound fault chain.

The pin table is the standard octal-latch map, and the LS and HC parts are identical on it: TI’s SN74LS373 sheet and TI’s SN74HC373 sheet give the same 20 pins in the same order, so the SN74HC373N the OpenTendo build specifies is a straight drop-in as far as the footprint is concerned. The EDC schematic draws U2 with the same numbering, which is what lets me call this verified rather than assumed.

One naming trap: TI calls the latch-enable pin C on the LS part and LE on the HC part. Same pin 11 either way, and on this board it is the PPU’s ALE output. Pin 1 is the active-low output control, which is a separate thing from the latch enable: outputs can be floated while the latch keeps its data.

Probing it: with the console running you should see ALE on pin 11 and traffic on both the D and Q sides. D pins moving with Q pins stuck is the chip; both sides stuck is more likely the PPU.

Lead order comes straight out of Panasonic’s own AN78xx/AN78xxF datasheet, which prints the legend against the package outline: 1 input, 2 common, 3 output. That is the standard 78xx arrangement, and the EDC power sheet draws the part the same way: rectified rail in on the left, +5 V out on the right, tab and centre lead to ground.

Pin 2 is also the metal tab, which is why the heatsink is at ground potential and why you can get away with bolting it straight to the shield can. Do not assume that on some other 78xx-family part: it is true for this one because ground is the centre lead.

The one diagnostic worth memorising: if all three terminals read 0 V, the input never arrived. That is a short or an open upstream, not a bad regulator, and swapping the 7805 will not fix it. The other one worth knowing is that a sagging regulator often measures fine unloaded: test it in circuit or bench-load it, do not trust a no-load reading.

AN7805 is one recorded example of what Nintendo fitted, not a uniform fact. Units shipped with various 78xx brands, and all of them share this lead order.

The NTSC RP2A03 and the PAL RP2A07 share this pinout; only the clock divisor and some APU/DMA behaviour differ. Pin 29 takes the 21.477272 MHz master clock (26.601712 MHz on PAL) and the core divides it by 12 (16 on PAL) internally.

Bench anchors I use on this chip: pin 40 is the 5.0 V rail check, pin 29 is TP1 for the master clock, pin 31 (M2) should show a 1.789773 MHz bus strobe, and pins 1 and 2 are where I look for APU life before chasing the audio chain. Pin 3 (/RST) sitting low or blinking at about 1 Hz is the lockout chip resetting the console, not a dead CPU.

Pins whose function I have cross-checked against the EDC schematic sheet are tagged verified; the address and data lines come from the NESdev pinout alone and are tagged single-source.

The composite PPUs (2C02 NTSC, 2C07 PAL) share this pinout. Pin 21 (VOUT) is the shifted analog composite output; on this console it feeds the 2SA937 emitter follower and then the modulator can. That is TP5 and it is the split point I use: good video at pin 21 but nothing at the RCA means the fault is the 2SA937, the modulator, or the coupling path, not the PPU.

Pin 39 (ALE) is what the 74LS373 latches on to demultiplex AD0-AD7 into the low VRAM address byte. Scrambled graphics with a game otherwise running points at the 373, the video RAM, or the PPU itself.

The RGB PPUs (2C03/2C04/2C05, arcade and PlayChoice) use the same pinout except that EXT0-2 become R, G, B, EXT3 becomes ground, and pin 21 becomes CSYNC. That matters if you are feeding a PlayChoice PPU into a mod.

This is the JEDEC 24-pin 2K x 8 static-RAM map, and I am publishing it because three sources that do not depend on each other agree pin for pin. Sony’s CXK5816PN/M datasheet covers the CXK5816SPS-15L that Console5 records in these sockets, and its own feature list states the part is pin compatible with MB8416A, HM6116 and uPD446. The Renesas 6116SA/6116LA datasheet (the modern part the OpenTendo rebuild specifies for U1 and U4) gives the identical map. And the EDC schematic draws both U1 and U4 with the same numbering.

What I have NOT confirmed: LH5216AD-10L and MN4216-20 against their own datasheets. I could not obtain either. They are recorded as observed parts in the same 6116-class socket, so treat them as very likely rather than proven, and read the marking on the chip in front of you before you probe.

Footprint history worth knowing before you order a donor part: boards up to NES-CPU-05 take narrow DIP only, and NES-CPU-06 onward accept either narrow DIP or standard-width DIP. DIP-24 6116-type SRAM is essentially gone from franchised distribution, so a donor board is usually the fast answer.

The two positions differ only in what drives the control pins. U1 is CPU work RAM: /WE follows CPU R/W and /CE is decoded by the 74LS139 at U3. U4 is the nametable RAM, and the cartridge decides how it mirrors: the cart drives CIRAM A10 into A10 from cart edge pin 22 and enables the chip through CIRAM /CE on cart edge pin 57. That is why a mirroring fault follows the cart, not the console.