Famicom Family and PAL NES Repair Reference

This is my companion page to the NES front-loader reference. The Japanese Famicom and its relatives share the same brains as the American NES: the same RP2A03 CPU, RP2C02 PPU, the same address decode and controller readout. So instead of repeating what I already covered there, this page documents only what is different on the siblings, and there is more of it than people expect. If a procedure is shared (corrosion cleanup, general recap approach, bench testing method), I link back to the front-loader page rather than saying it twice.

The machines covered here:

Famicom HVC-001, the original 1983 red-and-white console with hardwired controllers and RF-only output.
AV Famicom HVC-101, the 1993 redesign that adds composite video and drops the hardwired pads.
Sharp Twin Famicom, an all-in-one Famicom plus Disk System in one case.
Famicom Disk System (FDS), the RAM adapter and Mitsumi disk drive that plug into a Famicom.
PAL NES-001, the European front-loader, which is mostly the American machine with a few region traps.

The American front-loader is my daily bench work; these Japanese and PAL siblings come across it less often, so the procedures below lean harder on documented references than on a stack of my own repairs, and I have cited them as such. The method is the same method I trust; the failure-rate claims are the community’s, and I say so where it matters.

Safety first: the DC power trap

Read this before you plug in anything. This is the single most important difference from the American NES, and getting it wrong is instantly fatal to the console.

The American NES-001 takes 9 V AC and rectifies it onboard with a full bridge, so it does not care about polarity and shrugs off a lot of adapter mistakes. The Famicom family does none of that. It takes DC input, it has no onboard bridge rectifier, and the polarity is not even uniform across the family. The Twin Famicom is wired the opposite way from everything else.

Console	Adapter	Rating	Polarity	Barrel
Famicom HVC-001	HVC-002	DC 10 V, 850 mA	center-NEGATIVE	5.5 / 2.1 mm
AV Famicom HVC-101	HVC-002	DC 10 V, 850 mA	center-NEGATIVE	5.5 / 2.1 mm
Famicom Disk System	HVC-025	DC 9 V, 400 mA	center-NEGATIVE	5.5 / 2.1 mm
Twin Famicom	AN-500 (part UADP-0041CEZZ)	DC 7.6 V, 1.25 A	center-POSITIVE	5.5 / 2.5 mm
PAL NES-001	NES-002E	9 to 9.8 V AC, 1.3 A	none (AC, onboard bridge)	(barrel N/A)

Two things will hurt a Famicom:

Reversed DC. On a bare HVC-001 the DC jack feeds the 7805 regulator almost directly, so reversed polarity is destructive. The AV Famicom and the FDS power board each carry a single series protection diode, which usually makes a reversed hookup inert rather than fatal on those two. That diode is a single diode, not a bridge, so it protects against reverse DC but does not make the console AC-tolerant.
AC into any of them. Feeding an American NES adapter (which is AC) into a Famicom is the classic mistake, and it destroys all of them. Community references describe the regulator failing violently and instantly, because the AC hits the 7805 unrectified. That an AC brick is not harmless is itself the proof that no bridge rectifier exists anywhere in this family.

No OEM document I could find states the polarity of any of these consoles. The Famicom manual lists “DC10V 850mA” and shows no polarity glyph at all. Every polarity fact in the table above is from secondary sources, but each one is corroborated across several independent references and I found no dissent. Even so, the bench rule stands on its own:

Meter the barrel of any unknown import adapter before the first power-on, every time. Do not trust a label, a bin, or my table alone. A modern regulated replacement supply is the safe path: 9 V, center-negative for the Famicom, AV Famicom, and FDS, and the correct polarity and 2.5 mm pin for the Twin.

Common problems and fixes

Dead, or died right after a power swap

If a Famicom died the moment someone changed adapters, suspect polarity or adapter type first (see the safety block), then walk the power rail. The path is similar to the NES but the parts live in different places.

On the HVC-001 the regulator is not on the mainboard. The DC jack, power switch, and 7805 all live on the RF and power daughter-board, and regulated 5 V arrives at the mainboard through the P3 harness on pins 2 and 3. So if you are probing for 5 V, probe P3 first. If those pins read 0 V, the fault is upstream on the power board (the 7805, its input, or the jack), not on the mainboard. A 7805 that reads roughly the input voltage on all three pins has failed short and is passing its input straight through, which can put an over-voltage on the logic.

The Twin Famicom does not use a 7805 at all. Its regulator is an M5236L (IC201) and R211 is the 5 V adjustment pot, so on a Twin you set 5.0 V rather than swapping a fixed regulator.

Won’t boot, garbage, or works only after reseating a cart

The Famicom uses a 60-pin cartridge slot, not the American 72-pin ZIF connector. That is good news: it does not have the front-loader’s downward-push pin-bending problem, so the fix here is cleaning, not replacing. Clean the connector and the cartridge edge fingers with high-purity isopropyl alcohol, and look for corrosion under the connector. There is no equivalent to the front-loader connector refurbishment because there is no ZIF fatigue to correct. If a clean, known-good cart still fails, move on to the power rail and the logic, using the same testing approach from the front-loader page.

One RF-Famicom quirk that gets misdiagnosed as a fault: on some RF board revisions there is no picture at all unless a cartridge is inserted, because the video path is gated by a cart bridging two of the 60-pin contacts. A blank screen with no cart in is stock behavior on those units, not a failure.

Famicom Disk System will not load a disk

This is the dominant FDS complaint, and community references are unanimous that the usual cause is the drive belt. The Mitsumi Quick Disk mechanism uses a thin rubber belt, and after 30-plus years that belt stretches, goes gummy, or fully melts and half-welds itself to the pulleys. Sources call the belt the single most common failure in the whole family, and I flag that as a claim worth confirming on your own bench rather than assuming: open the drive and look. A healthy belt is a taut, clean loop. A dead one is slack, sticky, split, or shows up as a black smear on the pulleys.

The tell that separates a belt fault from an alignment fault: a belt problem means the disk barely spins or does not spin, and you often get ERR.02 at boot even with power confirmed. An alignment problem means the disk spins fine but misreads. If the motor energizes and the disk still will not turn, it is the belt.

Belt replacement is its own small project, covered below under “FDS drive service,” because a belt swap always disturbs the alignment and you have to re-verify it afterward.

FDS spins fine but throws read errors (ERR.21, ERR.22, ERR.27)

If the disk spins normally but the drive errors out, and especially if this started after a belt swap, you are into alignment, not the belt. But before you touch a single alignment screw, prove the media. Keep a known-good reference disk on the bench and test with it first, because a drive fault fails every disk while a media fault follows one disk from drive to drive. FDS disks have no shutter, the magnetic surface is exposed to dust and fingerprints, and the magnetic layer oxidizes and demagnetizes with age. Chasing alignment on a rotten disk is the most expensive time sink in FDS repair. If several disks read and one never does, stop working on the console and clean or rewrite the disk.

The FDS error codes have two published readings that do not fully agree (the BIOS-literal list versus the repair community’s bench heuristics), so treat a few codes as ambiguous. Broadly: ERR.21 and ERR.22 mean the drive cannot find the start of the data; ERR.23 through ERR.25 mean it found the start but is losing data further into the spiral; ERR.27 is commonly a worn felt pressure pad on the bench, though the ROM itself just means a premature block end. The alignment procedure below addresses all of these.

Wavy or dim video, hum, or buzz

As on the NES, the usual suspect is the electrolytic filter capacitors. The critical difference: do not reuse the NES cap list here. The Famicom family capacitor values and designators are board-specific, and I cover them under “Recap and parts” below. Community references single out particular caps as the common failures, and I treat those as leads to check rather than parts to replace on faith: inspect for bulging or leaking, scope the rail for ripple, and replace what actually reads bad.

One dim-picture case that is not a fault at all: early RF Famicom boards use a different video output resistor value than later boards, so a slightly dim color on an early board is stock. And the Twin Famicom has a factory audio layout that makes it sound muffled out of the box (a capacitor and resistor forming a low corner frequency). That dull sound survives a recap because the offending part is a ceramic, not an electrolytic, so a recap that “did not fix the dull audio” is not a failed recap.

Internal corrosion

Battery leaks and old liquid exposure leave corrosion just like on the front-loader, most often around the power and RF sections. I handle it the same way I describe on the front-loader page: neutralize the active corrosion, clean thoroughly with isopropyl alcohol, and seal the treated area.

FDS drive service: belt and alignment

The Famicom Disk System drive is the one genuinely different repair in this family, so it gets its own section. Twin Famicom owners: your integrated drive is the same mechanism and the same procedure.

The belt. No OEM belt spec exists, so this is derived from the drive geometry rather than measured off an original belt, and the published numbers are easy to misread. There are two different circumference figures floating around and they are not in conflict: one is the belt stretched and installed, the other is the belt relaxed. The stretched, installed path works out to roughly 245 mm (a fold of about 122 mm), while the relaxed loop is roughly 229 to 233 mm (a fold of about 115 to 116 mm). Buy an FDS-specific belt sold with a stated fold length, because unlabeled “FDS belts” have been sold at wrong sizes, and do not substitute generic Mobilon bands, which one detailed source found to be both too small and too rigid. Clean every trace of the old belt off the pulleys with isopropyl on a swab, and keep finger grease off the new belt and the pulleys or it will slip immediately.

The alignment. A belt swap always moves the calibration, so plan on re-checking four adjustments afterward. In order:

Spindle hub timing, held by a 1.5 mm hex set screw. This is the “which part of the spiral” adjustment.
Drive speed, set by a pot on the motor. The corrected target is 400 RPM measured at the disk-table shaft (roughly 800 RPM at the motor belt holder). Note that older references quote figures around 820 to 873 RPM at the shaft; those were retracted by their own author as a stroboscope-app harmonic error, so treat any 800-to-900 RPM reading at the shaft as a doubled artifact and calibrate to 400 with a real tachometer.
Head position, adjusted at the head screw to roughly 10.68 to 10.72 mm with a working tolerance around plus or minus 0.05 mm. A quarter turn moves it about 0.1 mm, so work in eighth-turn steps.
Pressure pad. Replace the felt if it is thin or worn (a common ERR.27 cause).

The one hard rule every source agrees on: adjust the head screw only. Do not touch the disk-clamp or spindle set screw once the drive is factory-aligned. A practical technique is to iterate the head in eighth-turn steps in one direction until ERR.21 flips to ERR.22, which marks one boundary of the good window, then reverse and bracket back into the center. Scrape any locking glue off the head screw with a perfectly fitting driver first, or you will strip it.

If you would rather remove the whole media-and-belt variable, an FDSKey or FDSStick emulates the drive from flash storage, which I cover under Mods.

Inside the family: what differs

A short tour of the deltas from the American front-loader, which makes the faults above make sense. Everything not listed here (the CPU, PPU, RAM map, controller readout) is identical to the front-loader and lives on that page.

Power is DC with no onboard bridge, and the regulator is not always on the mainboard (it is on the RF and power board on the HVC-001, and it is an adjustable M5236L on the Twin). This is the whole reason the polarity trap exists.
The cartridge bus is 60-pin, and it carries an expansion audio loop that the American 72-pin slot does not have. Pin 45 carries the console’s amplified audio out to the cartridge, and pin 46 carries audio back to the RF and audio section. Most carts simply bridge these two pins. Carts with their own sound hardware (the FDS RAM adapter, and mappers like VRC6, VRC7, MMC5, N163, and 5B) inject their audio into this loop, which is why Famicom expansion audio “just works” on real hardware and needs a mod on an American NES. If those two pins are open on the cart or the trace is broken on the console, the audio is silent, so check the loop before suspecting the sound chip.
Reset works differently. On the Famicom the PPU reset pin is tied to +5 V, so pressing Reset does not clear the screen the way it does on some machines. That is normal, not a stuck reset.
The pads run the same CD4021 shift register the NES uses, but hardwiring them changes the repair entirely. Controllers: How Five Consoles Read a Button compares this family with the SNES, Genesis and N64 approaches.
Controllers on the HVC-001 are hardwired, and controller 2 legitimately has no Select or Start buttons because a microphone occupies that space instead. A dead hardwired pad is usually harness flex fatigue where the cable enters the case. The AV Famicom’s detachable controller ports omit two data lines, so peripherals like the Zapper and Power Pad do not work on a stock AV Famicom. That is a design limitation, not a fault to chase.
Clocks are region-specific. NTSC-J machines run a 21.477272 MHz master crystal with the RP2A03 and RP2C02; PAL runs a 26.601712 MHz crystal with the RP2A07 and RP2C07. The region lock is baked into the chip divisors, so mixing region parts does not “mostly work,” it detunes the CPU speed, dot clock, and colorburst together. The NTSC-J oscillator has a real, adjustable trimmer (TC1), so a Famicom that will not color-lock on a picky TV may just want the trimmer set with a frequency counter, not a recap.
The PAL NES-001 is otherwise the American front-loader with two region traps: PAL-A and PAL-B use different, mutually incompatible lockout chip codes (a 1 Hz blink on the “wrong” PAL cart is a region mismatch, not hardware), and some PAL decks have controller-port protection diodes that can make otherwise-good NTSC pads read as dead. Its power path is the American AC-plus-onboard-bridge design, so do not carry Famicom DC and polarity logic over to a PAL NES.

Mods worth knowing

I do not reproduce anyone’s install guide. This is an orientation to what is worth doing and where to get the real instructions.

Composite / AV mod (RF Famicom only). The HVC-001 has no composite output at all, so adding it is the headline mod. It taps composite video off PPU pin 21 through a small transistor amplifier, with audio off the cart-audio pin. Do not ever destroy PPU pin 21, because a future RGB install needs it too. The low-labor path is a drop-in power-and-AV replacement board (for example the Backoffice Power VAMP), which is fully reversible and needs no case cutting. The AV Famicom and Twin already have composite, so this mod does not apply to them. Reference: nesdev PPU pinout (VOUT / composite amp).
RGB output: NESRGB. Tim Worthington’s board does RGB, S-video, and composite with no lag, and it fits every machine in this family via a per-console adapter board (the main board is the same across consoles; only the small adapter differs). The AV Famicom is the cleanest and most profitable host because its Multi Out needs no case cutting. As of the version 5 board (2026), the encoder moved into FPGA logic and the output set grew to composite, S-video, RGB, and component. One caution that only becomes visible after an RGB install: a G-revision-or-earlier PPU has a known speckle defect on RGB, so read the PPU revision before quoting the job. Reference: etim.net.au NESRGB and its Famicom install guide.
HDMI: Hi-Def NES. Kevtris’s kit gives a lag-free digital picture, but it does not fit every machine in this family: the original Famicom’s chip revisions are not supported, the AV Famicom and PAL NES are, and the Twin is untested. Confirm compatibility for your exact machine first. Reference: ConsoleMods: Hi-Def NES.
Region and lockout. This is a non-issue on the Famicom family, which has no lockout chip at all. It only matters on the PAL NES, where the fix is the standard CIC handling covered on the front-loader page.
FDS drive emulation. An FDSKey or FDSStick replaces the disk media entirely with flash storage, which removes the belt, alignment, and rotting-disk variables from a resale unit in one move. Reference: FDSStick.

For a broader mod orientation, RetroRGB’s NES mods index is the best single jumping-off page and covers the Famicom family too.

Recap and parts

The one rule to carry away from this section: the Famicom family caps are board-specific, and reusing an American NES cap kit will put wrong values in the wrong places. Identify your exact board by its silkscreen before you order.

Community references point at a handful of usual-suspect electrolytics per board: the HVC-002 power brick’s large filter cap, roughly 1000 uF filter caps on the Famicom and AV Famicom mainboards, and a 2200 uF main filter on the Twin’s power board. I treat these as parts to inspect and test, not parts to swap on faith. There is one value trap on the AV Famicom worth calling out: at least one position must stay at its small original value (a 47 uF), so do not “round up” every cap when you recap.

A couple of practical notes that carry over from my general recap and testing method (full version on the front-loader page):

When you replace a ceramic capacitor with a modern MLCC, remember that MLCC capacitance drops under DC bias, sometimes dramatically. Do not blindly swap a ceramic for a same-nameplate part in a filtering or timing position without accounting for the derating.
The Twin Famicom’s regulator is adjustable (R211), so after any power-board work, set 5.0 V rather than assuming it.

The hard data behind all of the above (the per-board capacitor maps, the non-cap consumables, the chip and connector pinouts, and the schematic facts) is tabled in the sections that follow. Long per-item notes fold away to keep it readable; expand any of them for the full detail. Because these machines come across my bench less often than the American front-loader, nothing in those tables is tagged as my own measurement: every row is doc-grounded and cites where it came from, and where two sources disagree I say so rather than picking a winner.

If you would rather buy a console that has already had this work done, everything I restore is in the shop. I will link specific Famicom-family service and RGB-mod listings here as those pages firm up.

Capacitor lists

The per-revision electrolytic maps. Watch the board column: the Famicom’s mainboard and its RF/power daughterboard run independent, colliding designator sequences, and that is exactly how a wrong cap ends up in a wrong hole.

HVC-CPU-07 Famicom HVC-001: early boards (HVC-CPU-01 … -08), 1983-88, RF only

Board p/n: HVC-CPU-01 … -05 (1983-84) · HVC-CPU-06 (1984, SMD RAM) · HVC-CPU-07 (1984-88, by far the most common) · HVC-CPU-08 (rare SMD-RAM -07 variant)

Mainboard (HVC-CPU-07) — electrolytics

Desig	Value	V	Substitute	Note
C1	0.47µF	16V	0.47µF ≥25V electrolytic or film	the reset cap, across SW1 ^{single source}^{console5-fc,fc-oem}
notes on C1 Sits in parallel with the reset switch, both sides to ground. A leaky part here gives you a console that resets on its own or refuses to come out of reset cleanly.
C2	1µF	50V	1µF ≥50V	audio-amp coupling into the U7 40H368 inverter stage ^{single source}^{console5-fc,fc-oem}
C19	1µF	50V	1µF ≥50V	^{single source}^console5-fc
C24	47µF	16V	470µF at 16-25V covers both readings	VALUE CONFLICT: the board silkscreen reads 470µF/6.3V, Console5's kit lists 47µF/16V ^{single source}^{console5-fc,board-scans}
notes on C24 A genuine disagreement between the bare-board scan and the published kit list. Read the board you actually have. When in doubt buy up: a 470µF at 16-25V is safe in either reading, and this is the mainboard’s own bulk position by the cart slot (it is absent on HVC-CPU-05, which has only C18/C20 68pF there).
C25	1000µF	6.3V	1000µF ≥10V low-ESR aluminium: keep this one electrolytic	BOARD-ASSIGNMENT CONFLICT: see notes before you order ^{single source}^{console5-fc,corpus}
notes on C25 Console5 lists C25 with the Famicom’s main PCB caps; my own reference library places the 1000µF bulk filter on the RF/power daughterboard instead (the two boards run independent, colliding designator sequences, which is exactly how a wrong cap ends up in a wrong hole). I have not resolved that from a board in hand, so I am flagging it rather than picking a side: identify which board your C25 is actually on before you order. Either way, this is a bulk reservoir. Sources say leave it aluminium rather than converting to ceramic.

RF / power daughterboard — electrolytics

Desig	Value	V	OEM p/n	Substitute	Note
C1	10µF	16V		10µF ≥25V	Console5 annotates this one explicitly as the Power PCB C1: not the mainboard's 0.47µF C1 ^{single source}^console5-fc
notes on C1 The two boards both have a C1. They are different parts and different values. This is the trap the colliding designator sequences set for you.

Controller 2 (microphone pad) — electrolytics

Desig	Value	V	OEM p/n	Substitute	Note
C7	0.33µF	50V		0.33µF ≥50V film	microphone coupling cap; Console5 lists it unnumbered as 'CONTROLLER 2' ^✓^{console5-fc,mic-schematic}
notes on C7 Two sources agree on this one: Console5’s controller-2 cap list and the Flashback microphone schematic, which numbers it C7.

HVC-002 AC adapter (external brick: shared with the AV Famicom) — electrolytics

Desig	Value	V	OEM p/n	Substitute	Note
C1	2200µF	16V		2200µF 16V low-ESR (a 3300µF 16V low-ESR is sold as the upgrade)	the cap everyone forgets, because it is outside the console ^{single source}^console5-fc
notes on C1 Console5 calls the brick’s internal filter a usual suspect. I have not bench-confirmed a failure rate for it, but the logic is sound and cheap: buyers judge a console on video noise, and this is the one reservoir that never gets replaced because nobody opens the adapter. No console cap kit includes it: order it separately.

HVC-CPU-GPM Famicom HVC-001: GPM boards (Ground Plane Method), 1988-93

Board p/n: HVC-CPU-GPM-01 (1988) · HVC-CPU-GPM-02 (1989-93, the final Famicom rev)

Mainboard (HVC-CPU-GPM-02, RF/power board soldered on) — electrolytics

Desig	Value	V	Substitute	Note
C1	10µF	50V	10µF ≥16V (Console5 notes 16V is fine)	^{single source}^console5-fc
C2	1µF	50V	1µF ≥50V	^{single source}^console5-fc
C7	1µF	50V	1µF ≥50V	^{single source}^console5-fc
C8	0.47µF	50V	0.47µF ≥50V	^{single source}^console5-fc
C21	47µF	16V	47µF ≥25V	^{single source}^console5-fc
C22	1000µF	6.3V	1000µF ≥10V low-ESR aluminium	the GPM-era bulk filter: sources call this one a usual suspect ^{single source}^{console5-fc,corpus}
notes on C22 This is the GPM equivalent of the earlier boards’ 1000µF. On a GPM board the RF/power section is soldered directly to the mainboard, so the main-versus-power-board designator confusion that dogs the HVC-CPU-07 does not really arise here. Sources single this position out as a common failure. I have not independently confirmed a failure rate, so treat it as the first thing to test rather than a part to replace on faith: look for bulge or leakage and scope the rail for ripple.

Controller 2 (microphone pad) — electrolytics

Desig	Value	V	OEM p/n	Substitute	Note
C7	0.33µF	50V		0.33µF ≥50V film	microphone coupling cap ^✓^{console5-fc,mic-schematic}

HVCN-CPU-01 AV Famicom HVC-101: Dec 1993 to 2003, composite Multi Out, detachable pads

Board p/n: HVCN-CPU-01 (1993-95) · HVCN-CPU-02 (1995-2003)

Mainboard (HVCN-CPU-01) — electrolytics

Desig	Value	V	Substitute	Note
C1	1µF	50V	1µF ≥50V	^{single source}^console5-fc
C4	1µF	50V	1µF ≥50V	^{single source}^console5-fc
C5	220µF	6.3V	220µF ≥10V	^{single source}^console5-fc
C13	1000µF	25V	1000µF 25V low-ESR aluminium	the AV Famicom's main input filter, right after the T1 common-mode choke ^{single source}^{console5-fc,corpus}
notes on C13 The DC path on an HVCN-CPU-01 is DCPLUG → T1 (a Taiyo Yuden CM08RB01 common-mode choke, not a rectifier) → C13 → U7 7805. There is no polarity protection on the -01 at all; the reverse-polarity diode arrives on the -02. Sources call this a usual suspect. As elsewhere on this page, I treat that as a lead to test rather than a part to swap blind.
C14	47µF	6.3V	47µF ≥10V: fit 47µF even if your board came with 1µF	VALUE TRAP: early -01 boards shipped 1µF/50V here; Nintendo revised it UP to 47µF ^{single source}^console5-fc
notes on C14 The one position in this family where “match what came out” is the wrong instinct. Early HVCN-CPU-01 builds carry 1µF/50V; later -01s and every subsequent AV Famicom revision carry 47µF, and Console5 recommends fitting 47µF even on an early board. Nintendo revised it upward for a reason. Also relocated between revisions: on the -02 this cap moves out from under the 7805 heatsink to a spot near the work RAM.
C15	0.47µF	50V	0.47µF ≥50V	^{single source}^console5-fc

AN-500/505 Sharp Twin Famicom: Famicom + FDS in one case, 1986-90

Board p/n: AN-500B / AN-500R (1986-87) · AN-505-BK / AN-505-RD 'Turbo Twin' (1987-90) · Main: DUNTK4786DE / DUNTK5630DE · Power: PWBF4785CEZZ · Disk: SP-394HB

Main PCB (DUNTK4786DE / DUNTK5630DE): Famicom core AND FDS silicon on one board — electrolytics

Desig	Value	V	Substitute	Note
C101	1µF	50V	1µF ≥50V	^{single source}^console5-tf
C102	1µF	50V	1µF ≥50V	^{single source}^console5-tf
C113	1µF	50V	1µF ≥50V	^{single source}^console5-tf
C118	0.47µF	50V	0.47µF ≥50V	^{single source}^console5-tf
C120	10µF	16V	10µF ≥25V	^{single source}^console5-tf
C123	0.1µF	50V	0.1µF ≥50V	^{single source}^console5-tf
C154	10µF	16V	10µF ≥25V	^{single source}^console5-tf

Power / AV PCB (PWBF4785CEZZ) — electrolytics

Desig	Value	V	Substitute	Note
C201	2200µF	16V	2200µF 16V low-ESR aluminium (Nichicon UVZ1C222MHD is the stock answer)	the Twin's main reservoir: sources call this the usual suspect on this board ^{single source}^{console5-tf,corpus}
notes on C201 Community references single this cap out as the Twin’s usual suspect. I have not confirmed that rate on my own bench, so it is a lead: inspect, scope the rail, replace what actually reads bad. Whatever you do on this board, re-set R211 to 5.00 V afterwards: the Twin’s regulator is adjustable and does not self-correct.
C203	470µF	6.3V	470µF ≥10V	^{single source}^console5-tf
C204	10µF	16V	10µF ≥25V	^{single source}^console5-tf
C206	220µF	6.3V	220µF ≥10V	^{single source}^console5-tf
C207	10µF	16V	10µF ≥25V	^{single source}^console5-tf
C210	1µF	50V	1µF ≥50V	^{single source}^console5-tf

Mitsumi Quick Disk drive (integrated): disk PCB SP-394HB — electrolytics

Desig	Value	V	Substitute	Note
C1	100µF	6.3V	100µF ≥10V	do these while the drive is open for the belt ^✓^{console5-tf,console5-fds}
notes on C1 The Twin’s drive is the same Mitsumi unit as the standalone FDS, so the same four caps and the same belt-and-alignment job apply.
C2	100µF	6.3V	100µF ≥10V	^✓^{console5-tf,console5-fds}
C3	100µF	6.3V	100µF ≥10V	^✓^{console5-tf,console5-fds}
C12	100µF	6.3V	100µF ≥10V	^✓^{console5-tf,console5-fds}

Player 2 controller (microphone pad) — electrolytics

Desig	Value	V	OEM p/n	Substitute	Note
C (mic coupling)	0.33µF	50V		0.33µF ≥50V film	Console5 lists it unnumbered under 'Player 2 Controller' ^{single source}^console5-tf
C (pad)	47µF	6.3V		47µF ≥10V	the Twin's pad 2 carries a second cap the Famicom's does not ^{single source}^console5-tf

HVC-022/023 Famicom Disk System: HVC-022 drive + HVC-023 RAM adapter

Board p/n: RAM adapter PCB: HVC-FMR-03 (two variants, differing only in the DRAM part) · Power PCB: FMD POWER-02 / -03 / -04 / -05 · Drive: Mitsumi Quick Disk

RAM adapter (HVC-FMR-03) — electrolytics

Desig	Value	V	Substitute	Note
C3	1µF	50V	1µF ≥50V	^{single source}^console5-fds
C4	47µF	16V	47µF ≥25V	^{single source}^console5-fds
C5	1µF	50V	1µF ≥50V	^{single source}^console5-fds

Power PCB (FMD POWER-0x) — electrolytics

Desig	Value	V	Substitute	Note
C1	100µF	25V	100µF ≥25V	^{single source}^console5-fds
C2	47µF	16V	47µF ≥25V	^{single source}^console5-fds
C3	100µF	25V	100µF ≥25V	^{single source}^console5-fds
C6	10µF	16V	10µF ≥25V	FMD POWER-05 boards only ^{single source}^{console5-fds,fds-power05}
notes on C6 Check which power board you have before ordering a kit. POWER-05 is a different design from -02/-03/-04: two ICs (a 6562 and a BU3208) rather than three or four, so a “missing” chip on a -05 is not a missing chip.

Mitsumi Quick Disk drive — electrolytics

Desig	Value	V	Substitute	Note
C1	100µF	6.3V	100µF ≥10V	do all four while the drive is open for the belt ^{single source}^console5-fds
C2	100µF	6.3V	100µF ≥10V	^{single source}^console5-fds
C3	100µF	6.3V	100µF ≥10V	^{single source}^console5-fds
C12	100µF	6.3V	100µF ≥10V	^{single source}^console5-fds

NESE-001 PAL NES-001 front-loader: 50 Hz silicon in a shared board design

Board p/n: NESE-001 (most of Europe) · NES-PAL-001 (early mainland EU) · NES-CPU-04 onward: the same silkscreen ladder as NTSC boards

Replacement parts

The non-cap parts a Famicom-family repair actually consumes, plus the ones that are donor-only.

Non-cap consumables

Function	OEM part	Why replaced	Substitute	Note
FDS / Twin drive belt	no OEM part number published; Console5 NIN-FDS-BELT (Mitsumi 2.8in Quick Disk, FLAT)	sources call this the single most common failure in the whole family	FDS-specific belt with a STATED fold length: flat, not the square Quick Disk belt sold for music gear	buy the FLAT one; the square SKU is for AKAI/Roland/Korg drives ^{single source}^{fds-belt,console5-fds,corpus}
notes Community references are unanimous that the aged belt is the usual cause of an FDS that will not load, and they call it the single most common failure across the family. I am carrying that as sources say rather than as my own measured failure rate: open the drive and look. A healthy belt is a taut clean loop; a dead one is slack, sticky, split, or a black smear welded to the pulleys. No OEM dimension spec exists anywhere. The published numbers are derived from drive geometry, and there are two of them that people mistake for a contradiction: the installed, stretched path is about 245 mm (fold about 122 mm) and the relaxed loop is about 229 to 233 mm (fold about 115 to 116 mm). Those are the same belt in two states. Buy one sold with a stated fold length: the same author who published the geometry previously circulated a 90 mm fold and has retracted it, so unlabelled bench-stock “FDS belts” are suspect. Do not substitute Mobilon bands: the detailed teardown that tested them found them simultaneously too small and too rigid, and finger grease picked up during the job transfers to the pulley and makes them slip immediately. Buy in tens. Every FDS and every Twin that comes in wants one, and the swap forces the full four-point re-alignment anyway.
FDS drive pressure-pad felt	none: cut from felt or cotton stock	worn or missing pad is a documented ERR.27 cause	felt/cotton pad cut to fit the spring arm opposite the head	inspect it during every belt job: cheapest thing to fix while the drive is already apart ^{single source}^{fds-belt,console5-fds}
notes No commercial replacement exists that I could find; techs cut their own. The pad lives on the spring-loaded arm opposite the read head. It is the most annoying thing to discover after you have closed the drive.
+5V regulator (Famicom / AV Famicom / FDS)	7805 (TO-220)	failed short passes the raw ~10 V input straight to the logic	STMicro L7805CV, MC7805ABT, or any reputable 5 V TO-220 78xx	keep the heatsink; on an HVC-001 it is on the RF/power board, not the mainboard ^{single source}^{console5-fc,corpus}
notes Replace the fuse and at least one input cap along with it, and check what the over-voltage may have taken with it before declaring victory.
+5V regulator (Twin Famicom)	Mitsubishi M5236L (IC201, PWBF4785CEZZ)	obsolete adjustable regulator; a Twin reading low on the rail may just need R211 trimmed	NOS or donor board only: no franchised stock found	NOT a 7805. Re-set R211 to 5.00 V after any power-board work ^{single source}^console5-tf
notes Do not drop a fixed 7805 into this position without reworking the adjust network. Trim before you condemn.
60-pin cartridge connector	P1: 60-pin card edge, 2.54 mm pitch	rarely: it is a wiping friction connector with no ZIF fatigue. Replace only if physically damaged	Muramasa Entertainment 'Famicom Edge Connector' or generic 60-pin slots; test-fit before a fleet buy	clean, do not replace. This is not the NES 72-pin ZIF problem ^{single source}^{corpus,nesdev-cart}
notes The single best piece of news about working on Famicoms instead of NES front-loaders. Clean the slot and the cart fingers with high-purity isopropyl and check for corrosion underneath. Aftermarket listings tend to give no pitch spec or fitment confirmation, so test-fit one before committing to a batch.
Controller-2 microphone capsule	none available	dead or noisy mic on an HVC-001 / Twin pad 2	any electret capsule of the right geometry that takes a 2.2 kΩ load at 5 V	fit-and-listen, not spec-match: the original's characteristics are not published ^{single source}^{mic-schematic,corpus}
notes Rule out the cartridge first: there is a documented case of mic-borne digital noise that survived a full recap and a pad clean and turned out to be an NES EverDrive in a 60→72 adapter.
Controller conductive pads / membranes	RetroFixes Famicom conductive-pad kits, sold in separate P1 and P2 (no Start/Select) variants	unresponsive buttons on hardwired pads	generic Famicom pad rubber (AliExpress / eBay)	pad 2 legitimately has no Select or Start: do not 'repair' a missing button ^{single source}^corpus
notes Because the pads are hardwired on the HVC-001 and the Twin you cannot swap-test a controller. A dead button is the conductive pad, the 4021 shift register, or flex fatigue in the cable where it enters the case.
Glue logic (bench spares)	40H368P (U7/U8), 74LS373 (U2), 74LS139 (U3)	controller/mic/expansion faults on an HVC-001 point at U8; address-decode faults at U2/U3	74HC368 / 74HC373 / 74HC139	the HC substitutes are documented as fine on PRE-GPM Famicoms; use LS parts on a GPM board ^{single source}^{corpus,console5-fc}
notes Silkscreen trap: HVC-CPU-07 boards silkscreen 74HC373 / 74HC139 but the one documented populated -07 BOM lists 74LS373 / 74LS139P. Either family works electrically, so match what is actually in the socket rather than what the legend asks for. U7 is doing double duty on an original Famicom: one of its inverter sections is the audio amplifier, run in its linear region with R7 = 100K of feedback. That is why a marginal U7 gives you distorted-but-present audio rather than silence.
Work / video SRAM	MB8416A-15L, XRM6216-10, TMM2015BP-15, BR62168-10LL (2K x 8)	bench spares; garbled graphics or no-boot	any 16 Kbit (2K x 8) 5 V SRAM at 200 ns or faster that fits	DIP-24 6116-class parts are effectively gone from distribution: SOIC + adapter or donor board ^{single source}^corpus
CPU / PPU / FDS ASIC	RP2A03 (E/G/H), RP2C02 (B/C/D/E/G/H), RP2C33 / RP2C33A	donor parts only: none of these are manufactured	2A03 E/G/H interchange; 2C02 revisions interchange but AVOID RP2C02A; RP2C33 variants interchange (the -02 boots a different logo)	a harvested PAL set (RP2A07 + RP2C07 + 26.601712 MHz crystal) is sold as a unit for region conversion ^{single source}^{corpus,nesdev-ppuvar}
notes Two revision facts that change a quote. Swapping an original pre-recall 2A03 out is an upgrade on a square-button Famicom, since that die has no looped-noise APU mode. And RP2C02A is the one to avoid: it has asynchronous PPUMASK/PPUCTRL and different VRAM access, and it is the most likely culprit behind early-Famicom flash-cart incompatibility. Check the 5 V rail on an unrecapped board before condemning the cart, though.
AV Famicom 'JIO' PIO	BU3266 / BU3270 (U3, HVCN-CPU-01)	no modern substitute exists	donor AV Famicom or NES-101 top-loader (the two JIO parts interchange); or discrete: 2x 40HC368 + 74LS139 + 74HC04 + 10K pull-ups	board-level donor drop-in is single-source; the part-to-part substitution is what NESdev states ^{single source}^{nesdev-jio,corpus}
Obsolete discretes	Q1 2SA937 (video buffer), Q2/Q3 2SC2021 (oscillator/RF drive)	video output faults; oscillator faults	no verified modern drop-in; 2N3906 substitutes for the 2SA937 in the composite-amp circuit but has a DIFFERENT pinout	counting 2SC2021s is a board-ID tell: two = HVC-CPU-05/-07, one = GPM-02 ^{single source}^{nesdev-ppu,board-scans,corpus}
notes NESdev’s composite-mod circuit reuses the original 2SA937 rather than replacing it, and warns that a 2N3906 substitute has E/B/C in a different order. Get that backwards and you get no picture and a warm transistor.
Power supply	HVC-002 (Famicom + AV Famicom), HVC-025 (FDS), UADP-0041CEZZ (Twin)	the family's most destructive failure mode is the wrong brick, not a worn one	regulated 9 V / 1.5 A CENTRE-NEGATIVE for the Famicom, AV Famicom and FDS; correct polarity and a 2.5 mm pin for the Twin	meter every unknown import brick before first power-on. Never feed any of these an NES (AC) adapter ^✓^{junkerhq,retrogamesupply,famicomworld-pwr,famicomworld-fdspwr}
notes The original HVC-002 is linear and unregulated, so 12-14 V open-circuit on a genuine brick is normal, not a fault. Spec any replacement or dongle to the regulated equivalent (9 V), not to the 10 V nameplate. The Twin Famicom also ships a 100 V-mains brick. On 120 V or 230 V mains use a step-down or a correctly rated modern supply, not the original.

Chip & connector pinouts

The component library: each IC and connector defined once, with an interactive pin diagram and a folded pin table. The revision badge on each card shows which machine or board it applies to. The connectors are the interesting half here: the 60-pin cart slot, the DA-15 expansion port, the P3 power harness, the AV Famicom Multi Out, and the FDS drive cable are what you actually put a probe on.

Components & pinouts

Each part is defined once. The revision badge on every card shows exactly which board revision(s) it applies to.

Every diagram rotates and flips to match the board in front of you, zooms from a whole-package overview up to 3.2×, and saves at the orientation you are looking at — ↓ SVG matches the screen, and ↓ SVG (print) gives you the same drawing as ink on white. Both are vector, so print them at any size you like, which is the better route for the long connector pinouts since printing this page has to shrink them to fit the sheet. The # beside a part name links to that card, and the one in the pin panel links to a single pin — either link opens the card for whoever you send it to.

Microphone amplifier inverter (4069UB, in pad 2) 4069 / 4069UB CMOS hex inverter, 14-pin HVC-CPU-07 · HVC-CPU-GPM · AN-500/505 dip-14^{single source}^{ds-cd4069ub,mic-schematic,enri,corpus}#

One gate of a jellybean CMOS hex inverter, DC-biased as a linear amplifier. Both redraws of the pad-2 circuit put the mic on gate A: pin 1 in, pin 2 out

This is the amplifier in the pad-2 microphone circuit. See the microphone-circuit card for the surrounding network. It gets its own entry because unlike the rest of that circuit it is a jellybean with a published, standardised pinout: the table below is the TI CD4069UB Functional Diagram (SCHS054E), and the numbering is identical in every 14-pin package any vendor ships this part in.

Use the unbuffered type. A 4069UB run with a resistor from output back to input sits in its own linear region and works as a single-stage analogue amplifier; a buffered 4069 or a 4049/4050 will not behave the same way in that position. The same rule applies to the 74HCU04 in the Twin and the BU4069UB on the FDS RAM adapter.

Which gate. Both independent redraws of the pad-2 circuit (Flashback Vintage Electronics rev 7B and Enri’s control-pads sheet) show the mic feeding gate A, pin 1 in and pin 2 out, with the linear-bias resistor strapped pin 1 to pin 2. That matches the CD4069UB diagram (A = pin 1, output = pin 2). The two drawings disagree on the value of that bias resistor (rev 7B shows a 20 kΩ node, Enri shows 120 kΩ), and rev 7B’s own author annotates that corner of his schematic as unverified. Meter it before you replace it.

What I have not confirmed: the vendor marking or the physical package on a real pad-2 PCB. Neither drawing records it, and I do not have a mic pad open on the bench. The pin numbers are package-independent so the table holds either way, but do not read the DIP drawing as a claim that Nintendo used a through-hole part. Whether the remaining five gates are used or tied off is likewise uncaptured: check before you cut anything.

0° 1×

Click a pin to see its signal, net, and sources.

Interactive diagram needs JavaScript. The full pinout is in the table below.

Pin	Signal	Cat	Net	Note
1	1A (input)	signal	mic_amp_in	the microphone side: coupling cap and bias network land here ^{single source}
2	1Y (output)	signal	mic_amp_out	amplified mic out, toward the $4016 bit-2 line and the audio mix ^{single source}
3	2A (input)	signal	inv2_in	^✓
4	2Y (output)	signal	inv2_out	^✓
5	3A (input)	signal	inv3_in	^✓
6	3Y (output)	signal	inv3_out	^✓
7	VSS (GND)	gnd	gnd	^✓
8	4Y (output)	signal	inv4_out	note the ordering flips on this side: output is the LOWER pin number ^✓
9	4A (input)	signal	inv4_in	^✓
10	5Y (output)	signal	inv5_out	^✓
11	5A (input)	signal	inv5_in	^✓
12	6Y (output)	signal	inv6_out	^✓
13	6A (input)	signal	inv6_in	^✓
14	VDD (+5V)	rail	vcc	^✓

Nintendo 'JIO' custom PIO BU3266 / BU3266S / BU3270 / BU3270S HVCN-CPU-01 dip-32^{single source}^{nesdev-jio,consolemods-md,wikimedia-av}#

AV Famicom U3: absorbs the 74LS139 decoder, both 40H368 controller buffers, the 10K pull-ups and the data inverters. No modern replacement exists

The integration itself is confirmed four ways: the bare HVCN-CPU-01 scan silkscreens U3 JIO and carries no 74LS139 or 368 designator anywhere, the populated board photo shows a DIP laser-marked Nintendo / JIO A BU3270S, ConsoleMods describes the same combination, and NESdev documents the part. The pin table below is a single-source transcription of the NESdev BU3266 / BU3270 page and I have not cross-checked it against a second document or a chip on my bench: meter before you cut.

Which part you find is not predictable from the board revision: both BU3266 and BU3270 turn up on HVCN-CPU-01 boards. NESdev lists the two as interchangeable, which makes an NES-101 top-loader a donor for an AV Famicom’s U3 and vice versa. If the JIO is dead and you have no donor, the discrete-replacement BOM that gets quoted is 2x 40HC368 + 74LS139 + 74HC04 + 10K pull-ups.

Designator trap: HVCN-CPU-01 does have a U7. It is the 7805 regulator beside the DC plug, and it has no U8 at all. NESdev’s phrase “replaces the U3 (139) and the U7/U8 (368)” is describing the old HVC-CPU board’s designators, not this board’s.

Note pins 13 and 14 (P1 D3 / P1 D4). The chip has them, but the AV Famicom’s controller ports do not bring D3/D4 out to the jacks, which is why a Zapper or Power Pad does not work on a stock HVC-101.

0° 1×

Click a pin to see its signal, net, and sources.

Interactive diagram needs JavaScript. The full pinout is in the table below.

Pin	Signal	Cat	Net	Note
1	INV 3I	signal	inv3	inverter 3 input ^{single source}
2	INV 3O	signal	inv3o	inverter 3 output ^{single source}
3	M2	signal	m2	CPU clock in ^{single source}
4	A15	bus	abus	^{single source}
5	A14	bus	abus	^{single source}
6	A13	bus	abus	^{single source}
7	P1 D0	signal	p1d0	controller port 2 data 0 ^{single source}
8	P0 D0	signal	p0d0	controller port 1 data 0 ^{single source}
9	P1 D1	signal	p1d1	^{single source}
10	P0 D1	signal	p0d1	^{single source}
11	P1 D2	signal	p1d2	^{single source}
12	P0 D2	signal	p0d2	^{single source}
13	P1 D3	signal	p1d3	present on the chip but NOT wired to the HVC-101 jacks ^{single source}
14	P1 D4	signal	p1d4	present on the chip but NOT wired to the HVC-101 jacks: why the Zapper fails ^{single source}
15	GND	gnd	gnd	^{single source}
16	INV 1I	signal	inv1	inverter 1 input ^{single source}
17	INV 1O	signal	inv1o	inverter 1 output ^{single source}
18	CPU D4	bus	dbus	^{single source}
19	CPU D3	bus	dbus	^{single source}
20	CPU D2	bus	dbus	^{single source}
21	/INP1	signal	oe2	$4017 read strobe ^{single source}
22	/INP0	signal	oe1	$4016 read strobe ^{single source}
23	CPU D1	bus	dbus	^{single source}
24	CPU D0	bus	dbus	^{single source}
25	INV 2O	signal	inv2o	inverter 2 output ^{single source}
26	INV 2I	signal	inv2	inverter 2 input ^{single source}
27	CPU RAM /CE	signal	ram_ce	work-RAM chip enable (was the 74LS139's job) ^{single source}
28	PPU /CE	signal	ppu_ce	→ PPU pin 13 ^{single source}
29	/ROMSEL	signal	romsel	→ 60-pin cart pin 44 ^{single source}
30	INV 3B2	signal	inv3b2	^{single source}
31	INV 3B1	signal	inv3b1	^{single source}
32	+5V	rail	vcc	^{single source}

CPU + APU (RP2A03 NTSC / RP2A07 PAL) RP2A03 / RP2A03E / RP2A03G / RP2A03H (NTSC-J), RP2A07 (PAL) HVC-CPU-07 · HVC-CPU-GPM · HVCN-CPU-01 · AN-500/505 · NESE-001 dip-40^✓^{nesdev-cpu,nocash,fc-oem}#

Same 40-pin DIP on every machine here; the PAL RP2A07 is a socket-compatible swap that divides by 16 instead of 12

Two independent pin tables (the NESdev CPU pinout page and Martin Korth’s Everynes specs) agree on all 40 pins, which is why this one is tagged verified rather than single-source. The naming differs between them (NESdev’s AD1/AD2 are Korth’s ROUT/COUT; /OE1//OE2 are /JOY1//JOY2; OUT0-2 are J0-J2); the pin assignments do not.

Pins 1 and 2 are the analogue audio taps that make the Famicom’s mixer what it is: the factory schematic feeds pin 1 (pulse channels) through R4 = 20K and pin 2 (triangle / noise / DPCM) through R5 = 12K into a summing node, each loaded 100 Ω to ground, then couples that through C2 = 1 µF into one section of U7 (40H368) run as a linear amplifier with R7 = 100K of feedback. If a customer complaint is “one channel is quiet”, those resistors are where I would look before condemning the chip.

Pin 30 (TST) is grounded on every Famicom. Pulling it high does different things on different die revisions and none of them are things you want on a bench: leave it alone.

Revision matters more than the part number suggests. The earliest, pre-recall 2A03 has no APU “looped noise” mode at all, so a square-button Famicom that sounds wrong in Mega Man 2 may be correct by design. Read the chip, not the board number.

0° 1×

Click a pin to see its signal, net, and sources.

Interactive diagram needs JavaScript. The full pinout is in the table below.

Pin	Signal	Cat	Net	Note
1	AUX A (ROUT)	signal	aux_a	pulse channels 1+2 audio out: feeds R4 20K into the mixer ^✓
2	AUX B (COUT)	signal	aux_b	triangle / noise / DPCM audio out: feeds R5 12K into the mixer ^✓
3	/RST	signal	rst	active-low; pulled low by SW1 with C1 0.47 µF across the switch ^✓
4	A0	bus	abus	^✓
5	A1	bus	abus	^✓
6	A2	bus	abus	^✓
7	A3	bus	abus	^✓
8	A4	bus	abus	^✓
9	A5	bus	abus	^✓
10	A6	bus	abus	^✓
11	A7	bus	abus	^✓
12	A8	bus	abus	^✓
13	A9	bus	abus	^✓
14	A10	bus	abus	^✓
15	A11	bus	abus	^✓
16	A12	bus	abus	^✓
17	A13	bus	abus	^✓
18	A14	bus	abus	^✓
19	A15	bus	abus	not brought out to the 60-pin cart bus: /ROMSEL is how a cart sees it ^✓
20	GND	gnd	gnd	^✓
21	D7	bus	dbus	^✓
22	D6	bus	dbus	^✓
23	D5	bus	dbus	^✓
24	D4	bus	dbus	^✓
25	D3	bus	dbus	^✓
26	D2	bus	dbus	^✓
27	D1	bus	dbus	^✓
28	D0	bus	dbus	^✓
29	CLK	signal	clk	21.477272 MHz master clock on NTSC-J; 26.601712 MHz on a PAL RP2A07 ^✓
30	TST	signal	tst	grounded on every Famicom: do not lift it ^✓
31	M2 (PHI2)	signal	m2	CPU clock out; goes to 60-pin cart pin 32 ^✓
32	/IRQ	signal	irq	active-low, internal pull-up ^✓
33	/NMI	signal	nmi	active-low; driven by PPU pin 19 ^✓
34	R/W	signal	rw	^✓
35	/OE2 (/JOY2)	signal	oe2	$4017 read strobe: joypad 2 output enable ^✓
36	/OE1 (/JOY1)	signal	oe1	$4016 read strobe: joypad 1 output enable ^✓
37	OUT2	signal	out2	$4016 write bit 2 ^✓
38	OUT1	signal	out1	$4016 write bit 1 ^✓
39	OUT0	signal	out0	$4016 write bit 0: the controller strobe ^✓
40	+5V	rail	vcc	^✓

PPU (RP2C02 NTSC / RP2C07 PAL) RP2C02 / 2C02A-H (NTSC-J), RP2C07 / 2C07A-0 (PAL) HVC-CPU-07 · HVC-CPU-GPM · HVCN-CPU-01 · AN-500/505 · NESE-001 dip-40^✓^{nesdev-ppu,nocash,enri}#

Pin 21 (VOUT) is the composite tap every AV and RGB mod needs: never destroy it. Pin 22 is tied hard to +5V on a Famicom

NESdev’s PPU pinout page and Korth’s Everynes specs agree on all 40 pins, and NESdev states explicitly that the composite PPUs 2C02 and 2C07 share this pinout, so the PAL part is the same card, not a guess.

Two Famicom-specific facts worth carrying to the bench. First, pin 22 (NESdev calls it /RST, Korth calls it /SYNC EXT) is tied directly to the +5 V rail on every Famicom, which is why holding Reset does not clear the screen the way it does on an American NES. That is stock behaviour, not a stuck reset line. Second, pin 21 (VOUT) is the shifted analogue composite output, and it is the single pin the whole composite-mod and RGB-mod economy hangs off. If a previous owner has cut or lifted it, an NESRGB install gets a lot harder: check it before quoting a job.

The EXT0-3 pins (14-17) are grounded on consumer consoles. The official RGB PPUs (RC2C03 in the Sharp C1, RC2C05-99 in the Famicom Titler) replace EXT0-2 with R/G/B and VOUT with CSYNC on the same 40-pin footprint, which is why an RGB PPU is a socket swap rather than a new board.

0° 1×

Click a pin to see its signal, net, and sources.

Interactive diagram needs JavaScript. The full pinout is in the table below.

Pin	Signal	Cat	Net	Note
1	CPU R/W	signal	rw	^✓
2	CPU D0	bus	cpu_dbus	^✓
3	CPU D1	bus	cpu_dbus	^✓
4	CPU D2	bus	cpu_dbus	^✓
5	CPU D3	bus	cpu_dbus	^✓
6	CPU D4	bus	cpu_dbus	^✓
7	CPU D5	bus	cpu_dbus	^✓
8	CPU D6	bus	cpu_dbus	^✓
9	CPU D7	bus	cpu_dbus	^✓
10	CPU A2	bus	cpu_abus	register select ^✓
11	CPU A1	bus	cpu_abus	register select ^✓
12	CPU A0	bus	cpu_abus	register select ^✓
13	/CS	signal	cs	from the 74LS139 decoder (from the JIO on an AV Famicom) ^✓
14	EXT0	signal	ext	grounded on consumer consoles; = R on an RGB PPU ^✓
15	EXT1	signal	ext	grounded; = G on an RGB PPU ^✓
16	EXT2	signal	ext	grounded; = B on an RGB PPU ^✓
17	EXT3	signal	ext	grounded; = GND on an RGB PPU ^✓
18	CLK	signal	clk	21.477272 MHz NTSC-J / 26.601712 MHz PAL ^✓
19	/INT (/VBL)	signal	nmi	open-drain VBlank → CPU /NMI pin 33 ^✓
20	GND	gnd	gnd	^✓
21	VOUT	signal	vout	shifted analogue composite video: the AV/RGB mod tap ^✓ Both sources describe the same 2SA937 emitter-follower buffer hanging off this pin.
22	/RST (/SYNC EXT)	rail	vcc	tied hard to +5V on every Famicom → the screen never clears on Reset ^✓
23	/WR	signal	ppu_wr	VRAM write ^✓
24	/RD	signal	ppu_rd	VRAM read ^✓
25	PPU A13	bus	ppu_abus	^✓
26	PPU A12	bus	ppu_abus	^✓
27	PPU A11	bus	ppu_abus	^✓
28	PPU A10	bus	ppu_abus	^✓
29	PPU A9	bus	ppu_abus	^✓
30	PPU A8	bus	ppu_abus	^✓
31	PPU AD7	bus	ppu_adbus	multiplexed address/data ^✓
32	PPU AD6	bus	ppu_adbus	^✓
33	PPU AD5	bus	ppu_adbus	^✓
34	PPU AD4	bus	ppu_adbus	^✓
35	PPU AD3	bus	ppu_adbus	^✓
36	PPU AD2	bus	ppu_adbus	^✓
37	PPU AD1	bus	ppu_adbus	^✓
38	PPU AD0	bus	ppu_adbus	^✓
39	ALE	signal	ale	address latch enable → the 74LS373 ^✓
40	+5V	rail	vcc	^✓

Famicom Disk ASIC RP2C33 / RP2C33A (64-pin) AN-500/505 · HVC-022/023 dip^{single source}^{console5-fds,console5-tf,corpus}#

Disk controller + DRAM controller + IRQ hardware + the FDS wavetable channel + the serial link to the drive. Pinout not captured

Sits at IC109 on the Twin Famicom main board and on the HVC-FMR-03 RAM adapter in a standalone FDS. It presents 8K CHR RAM at PPU $0000-$1FFF, 32K PRG RAM at CPU $6000-$DFFF and an 8K BIOS ROM at $E000-$FFFF, and its expansion audio mixes back through 60-pin cart pins 45/46.

No pin table here: I have not found a published 64-pin pinout for it. Donor parts only: RP2C33 01, RP2C33A-01A and RP2C33A 02 interchange, but the -02 boots a different (Twin Famicom) logo screen. Getting the 64-pin ASIC off a donor intact is the hard part of that job.

Diagnostic value anyway: a no-boot FDS whose drive sounds healthy is very often the RAM adapter’s SRAM or this ASIC, not the mechanism.

No pins captured yet — bench stub.

Work / video SRAM (2K x 8) MB8416A-15L, XRM6216-10, TMM2015BP-15, BR62168-10LL (6116-class) HVC-CPU-07 · HVC-CPU-GPM · HVCN-CPU-01 · AN-500/505 dip-24^✓^{ds-mb8416a,ds-tmm2015bp,console5-fc,console5-tf,corpus}#

Two of these on every board: U1 work RAM, U4 video RAM (Twin: IC105 / IC108). Jellybean 6116-class part, pinout read off the manufacturer datasheets

The pin table below is read off two manufacturer datasheets for two of the part numbers actually seen in these sockets: the Fujitsu MB8416A PIN ASSIGNMENT diagram and the Toshiba TMM2015BP PIN CONNECTION (top view). They agree pin-for-pin, so this is tagged verified rather than single-source. The only differences are naming: Fujitsu numbers the data bus I/O0-I/O7 and calls pin 18 /CE, Toshiba numbers it I/O1-I/O8 and calls pin 18 /CS. Same pin, same function. Fujitsu’s own datasheet also states the part is pin-compatible with the HM6116, TC5517 and µPD446, and both parts are plug-compatible with a 16K EPROM footprint.

The other two markings I have logged in these positions, XRM6216-10 and BR62168-10LL, I could not pull datasheets for. They are 6116-class by every other indication, but I have not verified their pinouts, so if that is what is on your board, check it against the table rather than assuming.

Sourcing note: any 16 Kbit (2K x 8) 5 V SRAM at 200 ns or faster that fits is the documented substitute. DIP-24 6116-class parts are essentially gone from franchised distribution, so it is SOIC-plus-adapter or a donor board. Some HVC-CPU-06 and -08 boards carry SMD RAM instead of through-hole.

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Interactive diagram needs JavaScript. The full pinout is in the table below.

Pin	Signal	Cat	Net	Note
1	A7	bus	abus	^✓
2	A6	bus	abus	^✓
3	A5	bus	abus	^✓
4	A4	bus	abus	^✓
5	A3	bus	abus	^✓
6	A2	bus	abus	^✓
7	A1	bus	abus	^✓
8	A0	bus	abus	^✓
9	I/O0	bus	dbus	Toshiba calls this I/O1: same pin ^✓
10	I/O1	bus	dbus	^✓
11	I/O2	bus	dbus	^✓
12	GND (Vss)	gnd	gnd	^✓
13	I/O3	bus	dbus	^✓
14	I/O4	bus	dbus	^✓
15	I/O5	bus	dbus	^✓
16	I/O6	bus	dbus	^✓
17	I/O7	bus	dbus	Toshiba calls this I/O8: same pin ^✓
18	/CE (/CS)	signal	ce	chip enable, active-low; Toshiba names it /CS ^✓
19	A10	bus	abus	^✓
20	/OE	signal	oe	output enable, active-low ^✓
21	/WE	signal	we	write enable, active-low ^✓
22	A9	bus	abus	^✓
23	A8	bus	abus	^✓
24	+5V (Vcc)	rail	vcc	^✓

60-pin Famicom cartridge slot P1: 60-pin card edge, 2.54 mm (0.1 in) pitch HVC-CPU-07 · HVC-CPU-GPM · HVCN-CPU-01 · AN-500/505 · HVC-022/023 edge-60^✓^{nesdev-cart,nocash,fc-oem}#

Carries the expansion-audio loop (45/46) and CartridgePresent (31); has NO CIC pins, NO EXP0-9 and NO system clock

Three sources agree on this table: the NESdev cartridge-connector page, Korth’s Everynes specs, and the Nintendo factory P1 pin table on the OEM mainboard schematic. Pin 1 is at the label-side left of the cartridge, looking into the connector.

Two things make this connector the real difference from the American 72-pin slot. First, cartridge audio: pin 45 carries the console’s already-amplified 2A03 audio out to the cart and pin 46 carries audio back in. Most carts simply bridge them; carts with their own synthesiser (the FDS RAM adapter, VRC6, VRC7, N163, MMC5, Sunsoft 5B) insert their output between the two. A cart that leaves 45-46 open is silent, and so is a console with a broken trace there: check the loop before suspecting the APU. The 72-pin NES bus has no such pins at all, which is the whole reason expansion audio needs a mod on an NES.

Second, pin 31. On some RF-modulator board revisions it connects only to the TV/Game switch, so the modulator passes video only if a cart bridges pin 30 to pin 31; on other revisions it is just the +5 V supply. A Famicom with no picture and no cart inserted may be behaving exactly as designed.

Mechanically this is good news: 2.54 mm pitch means standard 0.1 in card-edge stock is dimensionally correct, and it is a friction connector with real wiping action, so it does not develop the front-loader ZIF’s pin-bend fatigue. Clean it, do not replace it, unless the plastic is cracked.

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Interactive diagram needs JavaScript. The full pinout is in the table below.

Pin	Signal	Cat	Net	Note
1	GND	gnd	gnd	bridge-ok ^✓
2	CPU A11	bus	cpu_abus	^✓
3	CPU A10	bus	cpu_abus	^✓
4	CPU A9	bus	cpu_abus	^✓
5	CPU A8	bus	cpu_abus	^✓
6	CPU A7	bus	cpu_abus	^✓
7	CPU A6	bus	cpu_abus	^✓
8	CPU A5	bus	cpu_abus	^✓
9	CPU A4	bus	cpu_abus	^✓
10	CPU A3	bus	cpu_abus	^✓
11	CPU A2	bus	cpu_abus	^✓
12	CPU A1	bus	cpu_abus	^✓
13	CPU A0	bus	cpu_abus	^✓
14	CPU R/W	signal	rw	^✓
15	/IRQ	signal	irq	internal pull-up in the console; safe to leave floating ^✓
16	GND	gnd	gnd	bridge-ok ^✓
17	PPU /RD	signal	ppu_rd	^✓
18	CIRAM A10	signal	ciram_a10	nametable mirroring select, cart → console ^✓
19	PPU A6	bus	ppu_abus	^✓
20	PPU A5	bus	ppu_abus	^✓
21	PPU A4	bus	ppu_abus	^✓
22	PPU A3	bus	ppu_abus	^✓
23	PPU A2	bus	ppu_abus	^✓
24	PPU A1	bus	ppu_abus	^✓
25	PPU A0	bus	ppu_abus	^✓
26	PPU D0	bus	ppu_dbus	^✓
27	PPU D1	bus	ppu_dbus	^✓
28	PPU D2	bus	ppu_dbus	^✓
29	PPU D3	bus	ppu_dbus	^✓
30	+5V	rail	vcc	^✓
31	CartridgePresent / RF VCC	rail	rfvcc	on some RF-board revs this gates the modulator: no cart, no picture, by design ^✓ The OEM P1 table labels this RF VCC and traces it to P3 pin 4.
32	M2 (PHI2)	signal	m2	CPU clock; address valid while high, data at the falling edge ^✓
33	CPU A12	bus	cpu_abus	^✓
34	CPU A13	bus	cpu_abus	^✓
35	CPU A14	bus	cpu_abus	^✓
36	CPU D7	bus	cpu_dbus	^✓
37	CPU D6	bus	cpu_dbus	^✓
38	CPU D5	bus	cpu_dbus	^✓
39	CPU D4	bus	cpu_dbus	^✓
40	CPU D3	bus	cpu_dbus	^✓
41	CPU D2	bus	cpu_dbus	^✓
42	CPU D1	bus	cpu_dbus	^✓
43	CPU D0	bus	cpu_dbus	^✓
44	/ROMSEL	signal	romsel	NAND of M2 and CPU A15: the only way a cart sees A15 ^✓
45	Audio from 2A03	signal	snd_out	console → cart, already amplified. Half of the expansion-audio loop ^✓
46	Audio to RF	signal	snd_in	cart → console → P3 pin 5. Cut trace here = silent console ^✓
47	PPU /WR	signal	ppu_wr	^✓
48	CIRAM /CE	signal	ciram_ce	enables the console's internal 2K VRAM ^✓
49	PPU /A13	signal	ppu_na13	inverted PPU A13 ^✓
50	PPU A7	bus	ppu_abus	^✓
51	PPU A8	bus	ppu_abus	^✓
52	PPU A9	bus	ppu_abus	^✓
53	PPU A10	bus	ppu_abus	^✓
54	PPU A11	bus	ppu_abus	^✓
55	PPU A12	bus	ppu_abus	^✓
56	PPU A13	bus	ppu_abus	^✓
57	PPU D7	bus	ppu_dbus	^✓
58	PPU D6	bus	ppu_dbus	^✓
59	PPU D5	bus	ppu_dbus	^✓
60	PPU D4	bus	ppu_dbus	^✓

72-pin NES cartridge slot (PAL front-loader) 72-pin card edge, 2.50 mm pitch: NOT 0.1 in NESE-001 edge-72^✓^{nesdev-cart,nocash}#

Adds CIC, EXP0-9 and SYSTEM CLK; DROPS cartridge audio entirely. 2.50 mm pitch means standard 0.1 in edge stock does not fit

Included here because the PAL front-loader is in scope on this page and because the 60-vs-72 comparison is the point. NESdev and Korth agree on the whole table.

What the 72-pin bus adds versus the Famicom’s 60: the four CIC lockout lines (34/35/70/71), EXP0-9 down to the console’s bottom expansion port, and SYSTEM CLK on pin 37. What it loses: cartridge audio in and out, and CartridgePresent. That missing audio pin is the hardware reason FDS, VRC6, VRC7, N163, MMC5 and Sunsoft 5B expansion audio plays on a Famicom and is silent on an unmodded NES.

Two mechanical traps. The pitch is 2.50 mm, not 0.1 in, so generic card-edge connectors accumulate enough error over 36 positions to short pins near the ends: there is no stocked distributor part. And PPU A10 and A11 (pins 63 and 62) are in reverse order on the NES, which trips people building adapters.

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Interactive diagram needs JavaScript. The full pinout is in the table below.

Pin	Signal	Cat	Net	Note
1	GND	gnd	gnd	bridge-ok ^✓
2	CPU A11	bus	cpu_abus	^✓
3	CPU A10	bus	cpu_abus	^✓
4	CPU A9	bus	cpu_abus	^✓
5	CPU A8	bus	cpu_abus	^✓
6	CPU A7	bus	cpu_abus	^✓
7	CPU A6	bus	cpu_abus	^✓
8	CPU A5	bus	cpu_abus	^✓
9	CPU A4	bus	cpu_abus	^✓
10	CPU A3	bus	cpu_abus	^✓
11	CPU A2	bus	cpu_abus	^✓
12	CPU A1	bus	cpu_abus	^✓
13	CPU A0	bus	cpu_abus	^✓
14	CPU R/W	signal	rw	^✓
15	/IRQ	signal	irq	^✓
16	EXP0	signal	exp	to the bottom 48-pin expansion port ^✓
17	EXP1	signal	exp	^✓
18	EXP2	signal	exp	^✓
19	EXP3	signal	exp	^✓
20	EXP4	signal	exp	^✓
21	PPU /RD	signal	ppu_rd	^✓
22	CIRAM A10	signal	ciram_a10	^✓
23	PPU A6	bus	ppu_abus	^✓
24	PPU A5	bus	ppu_abus	^✓
25	PPU A4	bus	ppu_abus	^✓
26	PPU A3	bus	ppu_abus	^✓
27	PPU A2	bus	ppu_abus	^✓
28	PPU A1	bus	ppu_abus	^✓
29	PPU A0	bus	ppu_abus	^✓
30	PPU D0	bus	ppu_dbus	^✓
31	PPU D1	bus	ppu_dbus	^✓
32	PPU D2	bus	ppu_dbus	^✓
33	PPU D3	bus	ppu_dbus	^✓
34	CIC to Pak	signal	cic	lockout: absent on every 60-pin console ^✓
35	CIC to MB	signal	cic	lockout ^✓
36	+5V	rail	vcc	^✓
37	SYSTEM CLK	signal	sysclk	26.601712 MHz on a PAL deck; 60-pin has no equivalent ^✓
38	M2	signal	m2	^✓
39	CPU A12	bus	cpu_abus	^✓
40	CPU A13	bus	cpu_abus	^✓
41	CPU A14	bus	cpu_abus	^✓
42	CPU D7	bus	cpu_dbus	^✓
43	CPU D6	bus	cpu_dbus	^✓
44	CPU D5	bus	cpu_dbus	^✓
45	CPU D4	bus	cpu_dbus	^✓
46	CPU D3	bus	cpu_dbus	^✓
47	CPU D2	bus	cpu_dbus	^✓
48	CPU D1	bus	cpu_dbus	^✓
49	CPU D0	bus	cpu_dbus	^✓
50	/ROMSEL	signal	romsel	^✓
51	EXP9	signal	exp	^✓
52	EXP8	signal	exp	^✓
53	EXP7	signal	exp	^✓
54	EXP6	signal	exp	the de-facto NES expansion-audio pin: the 60→72 adapter target ^✓
55	EXP5	signal	exp	^✓
56	PPU /WR	signal	ppu_wr	^✓
57	CIRAM /CE	signal	ciram_ce	^✓
58	PPU /A13	signal	ppu_na13	^✓
59	PPU A7	bus	ppu_abus	^✓
60	PPU A8	bus	ppu_abus	^✓
61	PPU A9	bus	ppu_abus	^✓
62	PPU A11	bus	ppu_abus	OUT OF ORDER on the NES: 62 is A11, 63 is A10 ^✓
63	PPU A10	bus	ppu_abus	OUT OF ORDER on the NES: see pin 62 ^✓
64	PPU A12	bus	ppu_abus	^✓
65	PPU A13	bus	ppu_abus	^✓
66	PPU D7	bus	ppu_dbus	^✓
67	PPU D6	bus	ppu_dbus	^✓
68	PPU D5	bus	ppu_dbus	^✓
69	PPU D4	bus	ppu_dbus	^✓
70	CIC +RST	signal	cic	^✓
71	CIC CLK	signal	cic	^✓
72	GND	gnd	gnd	bridge-ok ^✓

Detachable controller port (NES 7-pin) 7-pin male D-shell, jack on the console front HVCN-CPU-01 · NESE-001 header-7^{single source}^{nocash,nesdev-ctrl,nerdly-av}#

AV Famicom omits D3 and D4 at the jack: that is why the Zapper and Power Pad do not work on a stock HVC-101

Korth’s Everynes gives the numbered table; the NESdev controller-port page gives the same signal set as pin-position art without numbers, so I am calling the numbering single-source rather than pretending two sources confirm it.

All controller inputs are inverted inside the console: a LOW at the jack arrives at the CPU as a 1.

Two revision traps live on this connector. On the AV Famicom the D3 and D4 lines are simply not wired out, so light guns and the Power Pad fail on a stock HVC-101. That is a design limitation, not a fault to chase. On some PAL front-loaders there are protection diodes in the port: anode-to-jack on +5V/D3/D4/D0 and reversed series diodes on OUT and CLK. Those two lines then have to be pulled high by the controller, which the PAL NES-004E pad does with a 3.6 kΩ resistor each and a US NES-004 pad does not. Sources disagree on how universal this is: NESdev names FRA, HOL and NOE specifically and says early PAL units read either pad type, while ConsoleMods generalises it to all PAL. Test the unit in front of you rather than assuming by region.

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Interactive diagram needs JavaScript. The full pinout is in the table below.

Pin	Signal	Cat	Net	Note
1	GND	gnd	gnd	^{single source}
2	CLK	signal	clk	shift clock (CPU read of $4016 / $4017) ^{single source}
3	OUT0	signal	out0	latch / strobe ^{single source}
4	D0	signal	d0	serial data back from the pad ^{single source}
5	+5V	rail	vcc	^{single source}
6	D3	signal	d3	Zapper light / paddle button: NOT wired on the AV Famicom ^{single source}
7	D4	signal	d4	Zapper trigger / paddle position: NOT wired on the AV Famicom ^{single source}

Hardwired controller harness: pad 1 (P4) P4 mainboard header: 5-conductor, joypad 1 HVC-CPU-07 · HVC-CPU-GPM · AN-500/505 header-5^{single source}^{enri,nesdev-ctrl,corpus}#

5-conductor. Different pin order AND different wire colours from pad 2 (P5): the two harnesses are NOT interchangeable

Enri’s control-pads sheet gives the numbered P4 header directly, so this is no longer a stub. Pin 1 is the GND end of the header, pin 5 the +5 V end. Enri labels the read strobe “4016 CUP”, which is the $4016 read enable: the signal NESdev calls CLK on the 7-pin port and the CPU card calls /OE1.

Wire colours. NESdev’s controller-port page documents the factory colouring by signal: on pad 1, +5V white, OUT orange, D0 yellow, GND brown, CLK red. Joining that to Enri’s numbering by signal name gives the colour on each pin below. The colour source and the pin-number source are different documents, so treat the pairing as my join rather than as one OEM table, but the signal sets match one-for-one, five for five.

The two pads use different colours for the same signals: brown is GND here and the mic bit on pad 2. Do not colour-match across harnesses.

Because the pads are hardwired on the HVC-001 and the Twin you cannot swap-test a controller, which changes the diagnostic order. A dead button is the conductive pad, the 4021 shift register in the pad, or flex fatigue in the cable right where it enters the case: check the harness by wiggling before you open the pad.

Enri’s sheet is drawn for the HVC-001 mainboard. The Twin Famicom carries the same five signals to its pad-1 harness but I have not seen its board designators, so treat the numbering as Famicom-verified and Twin-assumed.

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Pin	Signal	Cat	Net	Note
1	GND	gnd	gnd	brown wire ^{single source}
2	D0	signal	joy1_d0	serial data back from the pad's 4021; yellow wire. Enri labels it '4016 D0' ^{single source}
3	OUT0	signal	out0	the $4016 write bit 0 strobe that latches the buttons; orange wire ^{single source}
4	CLK (/OE1)	signal	oe1	the $4016 read strobe that shifts the 4021; red wire. Enri labels it '4016 CUP' ^{single source}
5	+5V	rail	vcc	white wire ^{single source}

Hardwired controller harness: pad 2 (P5) P5 mainboard header: 6-conductor, joypad 2 + microphone HVC-CPU-07 · HVC-CPU-GPM · AN-500/505 header-6^{single source}^{enri,nesdev-ctrl,corpus}#

6-conductor: the extra one is the microphone bit, and it is pin 1. Neither the order nor the colours match pad 1

Same source as the pad-1 header: Enri’s numbered P5 block. The sixth conductor is the microphone, which the CPU reads as $4016 bit 2, and Enri puts it on pin 1: the opposite end of the header from where pad 1 puts its GND. This is why the two harnesses are separate cards rather than one: they are electrically different connectors, not two instances of one part.

Wire colours, from NESdev by signal, joined to Enri’s numbering the same way as pad 1: +5V blue, OUT yellow, D0 orange, GND red, CLK white, mic/D2 brown. Six signals, six colours, one-for-one. The join is mine.

Pad 2 legitimately has no Select or Start: the microphone occupies that space and those two buttons are physically absent, always reading not-pressed. Do not “repair” a missing Start button on a Famicom pad 2. The AV Famicom has no mic and no P5 harness at all: its controllers are removable and its ports omit D3/D4.

As with pad 1, the numbering is read off the HVC-001 sheet; the Twin carries the same signals but its own board designators are uncaptured.

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Pin	Signal	Cat	Net	Note
1	MIC IN (D2)	signal	mic	the microphone bit, read as $4016 bit 2; brown wire. This is the conductor pad 1 does not have ^{single source}
2	GND	gnd	gnd	red wire: red is GND here and +5V-adjacent nowhere else in this family ^{single source}
3	D0	signal	joy2_d0	serial data back from the pad's 4021; orange wire. Enri labels it '4017 D0' ^{single source}
4	OUT0	signal	out0	shared latch strobe with pad 1; yellow wire ^{single source}
5	CLK (/OE2)	signal	oe2	the $4017 read strobe; white wire. Enri labels it '4017 CUP' ^{single source}
6	+5V	rail	vcc	blue wire ^{single source}

DC power jack (HVC-002 input) 5.5 / 2.1 mm barrel, CENTRE-NEGATIVE HVC-CPU-07 · HVC-CPU-GPM · HVCN-CPU-01 header-2^✓^{fc-manual,junkerhq,famicomworld-pwr,retrogamesupply,nerdly-av}#

CENTRE-NEGATIVE, DC 10 V 850 mA. Reversed polarity on an HVC-001 or an HVCN-CPU-01 is destructive: there is no bridge and no protection diode on either

This is the single most expensive thing to get wrong on this platform, so it gets its own card. The centre pin is the NEGATIVE (0 V) terminal and the sleeve carries the positive rail: the opposite of most consumer barrel jacks, and the opposite of what a bin of generic adapters will hand you.

The Famicom takes DC. The American NES takes AC. The NES rectifies its input with a full onboard bridge and shrugs off polarity mistakes; the Famicom has no bridge at all, so the raw input lands almost directly on the 7805’s input pin. Two ways that ends badly: a centre-positive DC brick is destructive on a bare HVC-001 and on an HVCN-CPU-01 (the reverse- polarity diode only arrives on the HVCN-CPU-02 revision), and an AC brick destroys every machine in the family. The community reports of the regulator failing violently and instantly are themselves the proof no bridge exists.

Sourcing note on the ratings. The OEM manual’s ratings page gives DC10V 850mA, about 4 W, adapter HVC-002, and states no polarity at all. The centre-negative fact comes entirely from secondary sources, but four independent ones agree and an adversarial search turned up no centre-positive claim. The original HVC-002 is linear and unregulated, so 12-14 V open-circuit on a genuine brick is normal rather than a fault; the sanctioned modern replacement is a regulated 9 V / 1.5 A centre-negative supply, and that regulated figure is the one to design a USB-C dongle around, not the 10 V nameplate.

The Twin Famicom is the exception that makes the rule dangerous: it is DC 7.6 V at 1.25 A on a 5.5 / 2.5 mm barrel, and at least one respected source lists it as centre-POSITIVE. The opposite of everything else here. A 2.1 mm plug in the Twin’s 2.5 mm jack also makes intermittent contact. Meter the barrel of any unknown import brick before the first power-on, every time, and do not trust my table alone.

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Pin	Signal	Cat	Net	Note
1	Centre pin: 0 V (negative)	gnd	gnd	CENTRE-NEGATIVE: this is the return, not the supply ^✓
2	Sleeve: +10 V DC in	rail	vin	raw unregulated input to the 7805; 12-14 V open-circuit on a genuine linear HVC-002 is normal ^✓

Famicom expansion port (DA-15) P2: 15-pin male D-sub, front of the console (right side on the AV Famicom) HVC-CPU-07 · HVC-CPU-GPM · HVCN-CPU-01 · AN-500/505 header-15^✓^{nesdev-exp,nocash,enri}#

Nintendo calls it the 'expand connector'. Pin 2 SOUND is pre-mix on an RF Famicom and post-mix on an AV Famicom: the same pin hears different things

NESdev’s expansion-port page and Korth’s Everynes give the same 15 pins under different naming conventions (Korth’s port0/port1 are $4016/$4017, i.e. joypad 1 and joypad 2), so this one is verified rather than single-source.

This is the port that made the Famicom expandable despite its hardwired pads: third-party controllers, multitaps, the Famicom BASIC keyboard, the barcode reader, light guns and the Turbo File all hang off it. The Twin Famicom keeps it as side port “A”; the AV Famicom keeps it and moves it to the right-hand side.

The one bench subtlety is pin 2, SOUND. On an RF Famicom this tap sits before expansion audio is mixed in; on an AV Famicom it sits after. Same pin, different content, which matters when you are testing a peripheral that listens there. It is not, however, the cause of the AV Famicom’s loud-expansion-audio complaint; that comes from the mixing resistor network and JIO input loading, and the two should not be chained together.

On an HVC-001 the joypad-2 lines here are shared with the hardwired pad 2, so an expansion device on pin 8 can be disturbed by the built-in pad. Dead expansion-port pins on an original Famicom point at U8 (40H368), the same buffer the pad-2 microphone reads through, not at the connector.

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Interactive diagram needs JavaScript. The full pinout is in the table below.

Pin	Signal	Cat	Net	Note
1	GND	gnd	gnd	^✓
2	SOUND	signal	sound	analogue audio out: PRE-mix on the RF Famicom, POST-mix on the AV Famicom ^✓
3	/IRQ	signal	irq	direction depends on the cartridge; NESdev marks it uncertain ^✓
4	joypad 2 /D4	signal	p2d4	inverted input (Zapper button) ^✓
5	joypad 2 /D3	signal	p2d3	inverted input (Zapper light) ^✓
6	joypad 2 /D2	signal	p2d2	inverted input (barcode battler / Turbo File data in) ^✓
7	joypad 2 /D1	signal	p2d1	joystick 4 serial in / paddle ADC in ^✓
8	joypad 2 /D0	signal	p2d0	shared with the hardwired pad 2 on an HVC-001: expect interference ^✓
9	/OE joypad 2	signal	oe2	$4017 read strobe; used as a clock by pads ^✓
10	OUT2	signal	out2	$4016 write bit 2 (Turbo File data clock / tape out) ^✓
11	OUT1	signal	out1	$4016 write bit 1 ^✓
12	OUT0	signal	out0	$4016 write bit 0: the strobe for every pad ^✓
13	joypad 1 /D1	signal	p1d1	joystick 3 serial in / paddle button / tape in ^✓
14	/OE joypad 1	signal	oe1	$4016 read strobe ^✓
15	+5V	rail	vcc	^✓

FDS RAM adapter ↔ drive cable 12-pin flat cable, HVC-023 RAM adapter to the Mitsumi Quick Disk drive HVC-022/023 ffc-12^✓^{corpus,fds-power05}#

Pin 8 (motor VCC) has no wire in the cable: the drive powers its own motor from the base

Directions below are from the RAM adapter’s point of view. The signal set is corroborated from two directions: the NESdev disk-cable documentation and the reverse-engineered FMD POWER-05 board schematic’s P1.

The split this table gives you is the most useful triage in FDS work. A drive that never spins points at the power base, the motor supply and the VR1 speed loop: not at the cable. A drive that spins but never loads points at read data on pin 9, head alignment, or a slipping belt.

Note pin 8. The drive’s motor supply is electronically controlled on the drive side and the RAM adapter does not use it, so there is physically no wire for it in the cable. Do not chase continuity there.

Structurally, the drive connects only to the RAM adapter and never touches the Famicom’s cartridge bus at all. That is why an FDS fault is almost never a console fault.

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Pin	Signal	Cat	Net	Note
1	/write gate	signal	wgate	out, active low ^✓
2	VCC +5V	rail	vcc	^✓
3	/motor on	signal	motor_on	out, active low; on POWER-05 this also doubles as a crude battery-OK signal ^✓
4	VEE (GND)	gnd	gnd	^✓
5	/write data	signal	wdata	out, active low ^✓
6	busy	signal	busy	in, active high ^✓
7	write protect	signal	wprot	in, active high: ERR.03 lives here ^✓
8	motor VCC	rail	motor_vcc	NO WIRE in the cable: the drive supplies its own motor ^✓
9	read data	signal	rdata	in: spins-but-never-loads points here, or at alignment ^✓
10	/media set	signal	media_set	in, active low: the insertion switch; ERR.01 lives here ^✓
11	/ready	signal	ready	in, active low ^✓
12	/reset	signal	rst	out, active low ^✓

Nintendo Multi Out (AV Famicom) 12-pin Multi Out: the same physical connector as the Super Famicom / SNES HVCN-CPU-01 header-12^✓^{superfamicom-multiout,consolemods-multiout,nerdly-av}#

The shell has RGB, CSYNC and S-video pins but the HVC-101 drives NONE of them: only composite (9) and mono audio (11/12)

The 12-pin table is verified: two independent pinouts (the superfamicom wiki and ConsoleMods) agree on all twelve pins. What is connected on an HVC-101 is the part people get wrong.

The AV Famicom drives composite on pin 9 and audio on pins 11 and 12, and both audio pins carry the same mono signal, so “one channel is dead” on a unit that plays through both jacks is normal. The RGB pins (1/2/4), CSYNC (3) and the S-video pins (7/8) are physically present in the shell but are not connected, because the stock 2C02 has no RGB outputs at all. An S-video or RGB SCART cable shows no picture.

You cannot get RGB by wiring the empty Multi Out pins. RGB needs an RGB PPU or an NESRGB / Hi-Def board. The good news for the AV Famicom is that once you fit one, its outputs wire to the existing Multi Out with no case cutting, which is exactly why the HVC-101 is the most profitable host in this family for that mod.

Two caveats on the “not connected” pins. Pin 10 is the nominal +5 V rail, which is how the external HVC-103 RF modulator that plugs into the Multi Out is expected to be powered, but that +5 V is actually present on an HVC-101 rests on one source, so probe it before assuming it is live. And pin 3 is CSYNC on JP/NTSC gear but carries +12 V on PAL SNES and GameCube: irrelevant here since nothing drives it, but it matters the moment you reuse a SCART cable across consoles.

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Pin	Signal	Cat	Net	Note
1	R	signal	r	NOT CONNECTED on the HVC-101 ^✓
2	G	signal	g	NOT CONNECTED on the HVC-101 ^✓
3	CSYNC	signal	csync	NOT CONNECTED here; carries +12 V on PAL SNES / GameCube: watch your SCART cables ^✓
4	B	signal	b	NOT CONNECTED on the HVC-101 ^✓
5	GND	gnd	gnd	bonded bridge-ok ^✓
6	GND	gnd	gnd	bonded bridge-ok ^✓
7	Y (luma)	signal	y	NOT CONNECTED on the HVC-101 ^✓
8	C (chroma)	signal	c	NOT CONNECTED on the HVC-101 ^✓
9	CVBS (composite)	signal	cvbs	the only video the stock HVC-101 drives ^✓
10	VCC (+5V)	rail	vcc	powers the external HVC-103 RF modulator, but that it is actually LIVE on an HVC-101 is single-source. Probe it ^{single source}
11	Audio L	signal	audio	mono: same signal as pin 12 bridge-ok ^✓
12	Audio R	signal	audio	mono: same signal as pin 11 bridge-ok ^✓

Mainboard ↔ RF/power harness (P3) P3: 7-pin header on HVC-CPU-05 / -07; 4-pin on HVC-CPU-GPM-02 HVC-CPU-07 header-7^✓^{fc-oem,enri,board-scans}#

Probe pins 2 and 3 FIRST on a dead Famicom: the 7805 is not on the mainboard, and 0 V here means the mainboard is innocent

The most useful seven pins on an original Famicom. The DC jack, power switch, 7805 regulator, reservoir caps and RF modulator all live on the RF/power daughterboard, and regulated +5 V comes back to the mainboard over this harness. The bare HVC-CPU-07 board scan has no regulator footprint anywhere on it, only this header, so Console5’s “7805” entry for HVC-CPU-07 is a system-level statement, not a place to go looking.

Diagnostic consequence: a dead Famicom with a known-good HVC-002 is a power-board fault far more often than a mainboard fault. Probe P3 pins 2 and 3 for 5 V first. If they read 0 V, the suspects are the 7805, its input caps, the switch and the jack, and you can stop worrying about the logic.

Pin 4 is the other one worth knowing: RF VCC comes from 60-pin cart pin 31, which is why the modulator on some revisions passes video only with a cart inserted.

Applies to the 7-pin revisions only. The final revision HVC-CPU-GPM-02 carries a 4-pin P3 plus a direct-solder pad field, because the RF/power board is soldered straight to the mainboard from GPM-01 onward. Do not carry this numbering onto a GPM board: I have not captured the 4-pin mapping. The 5 V-on-2-and-3 diagnostic is a 7-pin-revision fact.

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Pin	Signal	Cat	Net	Note
1	GND	gnd	gnd	bridge-ok ^✓
2	VCC (+5V)	rail	vcc	regulated +5V arriving FROM the RF/power board: probe here first bridge-ok ^✓
3	VCC (+5V)	rail	vcc	same net as pin 2 bridge-ok ^✓
4	RF VCC	rail	rfvcc	mainboard → RF board; sourced from 60-pin cart pin 31, so it gates the modulator ^✓
5	AUDIO	signal	audio	mainboard → RF board, from 60-pin cart pin 46 (the expansion-audio return) ^✓
6	GND	gnd	gnd	bridge-ok ^✓
7	VIDEO	signal	video	mainboard → RF board, from the Q1 2SA937 buffer (R6/R12 junction) ^✓

Twin Famicom power-PCB supply connector J J: 8-pin, PWBF4785CEZZ power/AV PCB → main PCB AN-500/505 header-8^{single source}^console5-tf#

Bench-derived by Console5, not from a Sharp document: pin 6 is marked uncertain in the source itself. Ring it out before trusting it

Console5 publishes this as bench work on a real Twin Famicom rather than from a service manual, and the source itself puts a question mark against pin 6. I am carrying it as single-source and passing that caveat through rather than laundering it into a clean table.

What it buys you: on a Twin the video and audio leave the main PCB through this connector on their way to the rear RCA jacks, so a Twin with sound but no picture (or the reverse) has a small, well-defined harness to check. And +5 V arrives on pins 1 and 2 from the M5236L regulator, which is adjustable: R211 on the power PCB sets it. Always re-set 5.00 V after any power-board work on a Twin; it is not a fixed 7805 and it does not self-correct.

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Pin	Signal	Cat	Net	Note
1	+5V	rail	vcc	from IC201 M5236L; R211 sets this rail bridge-ok ^{single source}
2	+5V	rail	vcc	same net as pin 1 bridge-ok ^{single source}
3	GND	gnd	gnd	bridge-ok ^{single source}
4	Video	signal	video	to the rear RCA video jack ^{single source}
5	GND	gnd	gnd	bridge-ok ^{single source}
6	Audio (?)	signal	audio	UNCERTAIN: the source itself marks this one with a question mark ^{single source}
7	Power switch SW103	signal	sw103	bridge-ok ^{single source}
8	Power switch SW103	signal	sw103	bridge-ok ^{single source}

Twin Famicom power-PCB supply connector K K: 4-pin, PWBF4785CEZZ power/AV PCB → main PCB and disk drive AN-500/505 header-4^{single source}^console5-tf#

Console5 records destinations rather than signal names; pins 2 and 3 are common

The second Twin power-PCB harness. Console5 documents it as destination-to-destination rather than by signal, so that is how it is reproduced here. Pins 2 and 3 are noted as common in the source, which is a useful continuity check if you are tracing a Twin that powers the console but not the drive (or the other way round).

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Pin	Signal	Cat	Net	Note
1	→ Main PCB E11	signal	e11	^{single source}
2	→ Main PCB E12	signal	common23	common with pin 3 bridge-ok ^{single source}
3	→ Disk drive pin 16	signal	common23	common with pin 2 bridge-ok ^{single source}
4	→ Disk drive pin 17	signal	drv17	^{single source}

Controller-2 microphone circuit Electret capsule + 2.2 kΩ bias + 0.33 µF coupling + 4069 unbuffered inverter (in the pad) HVC-CPU-07 · HVC-CPU-GPM · AN-500/505 header^{single source}^{mic-schematic,console5-fc,corpus}#

Lives in the PAD, not the console. Reads as $4016 bit 2 and also bleeds into the audio mix. The AV Famicom has no mic at all

Pad 2 on an original Famicom and on a Twin has a microphone where Select and Start would be. Those buttons are physically absent and always read as not-pressed. The mic is read as a one-bit input on $4016 bit 2 and it also bleeds into the console’s audio output.

Circuit, from the Flashback Vintage Electronics schematic rev 7B: the capsule is biased through 2.2 kΩ to +5 V, its output couples through C7 = 0.33 µF into a 20 kΩ node feeding a 4069 unbuffered inverter used as the amplifier (that inverter now has its own card with a real pin table: it is a jellybean and there was no reason to leave it buried in prose); the console side sums it at U8 (40H368) and into the audio mix through C2 1 µF. The 2.2 kΩ bias and the 4069 amp are independently confirmed by a NESdev mic-restoration thread, and Console5’s controller-2 cap list confirms exactly one 0.33 µF / 50 V part, which is the coupling cap. A competing forum description of the circuit disagrees on the rest of the values, so treat anything beyond those three as unconfirmed and meter the pad.

Repair implications. Mic buzz lives on the pad-2 harness, not on the mainboard. A stuck mic presents as spurious $4016 bit-2 input. No OEM capsule is available; the documented approach is any electret of the right geometry that takes a 2.2 kΩ load at 5 V, chosen by fit-and-listen rather than spec-match. And before you touch the mic at all: Console5 documents a case where mic-borne digital noise survived a full recap and a pad clean, and turned out to be an NES EverDrive in a 60→72 adapter. Rule out the cart first.

No pins captured yet — bench stub.

RF / power daughterboard (video output chain) Two-piece 'first type' board or the later one-piece PCB; soldered down from HVC-CPU-GPM-01 HVC-CPU-07 · HVC-CPU-GPM header^{single source}^{enri,fc-oem,schenkzoola,board-scans,nesdev-ppu}#

Carries the DC jack, power switch, 7805, reservoir caps and the RF modulator. The mainboard has none of them

Not a connector, but it behaves like one on the bench: everything that kills an original Famicom lives here, and the mainboard gets +5 V back over P3.

The video chain differs by board. Both variants take PPU pin 21 (VOUT) into Q1, a 2SA937 emitter follower. On the two-piece “first type” board, R6 = 2.2K, the emitter network is R12 = 220 Ω, there is an explicit VIDEO tap, and the RF board couples through C1 = 1 µF with R1 = 10K and R2 = 1K. On the one-piece PCB, R6 = 150 Ω with an inline FC2 ferrite and C34 = 330 pF to ground, and the RF coupling is C1 = 10 µF with 10K. The practical read: a slightly different picture level between an early and a late board is stock, not a fault.

Which of those values you can lean on. The first-type figures now have a second source: schenkzoola’s KiCad Famicom schematic draws the same Q1 2SA937 off PPU pin 21 with R6 = 2.2K and R12 = 220 Ω, and draws the P3 harness as GND, +5 V, +5 V, +5 V, audio, GND, video. That is a redraw its author checked against the factory schematic rather than a fresh trace, so it is corroboration rather than an independent second observation, but it is a copy anyone can pull up and check. The one-piece PCB figures and everything inside the RF can itself are still one redrawn sheet each.

The RF board does no audio amplification at all: P3 pin 5 goes through a 0.1 µF coupling cap and a 12K series resistor straight into the modulator. All the audio gain is the U7 40H368 inverter on the mainboard.

One mod-relevant fact from NESdev: on HVC-CPU-01 through -08 there is no benefit to cutting PPU pins or foiling the PPU when adding composite, but on the GPM-01 and GPM-02 boards, isolating pin 21 from its original trace gives a visibly better picture. Worth knowing before you quote an AV mod on a late board.

The modulator can’s own internals are undocumented here, and that is a retrieval problem rather than a research one. A full reverse-engineering exists (lidnariq posted a PDF, a KiCad archive and a BOM to the NESdev forum in 2022), and the attachments cannot be downloaded. As of 2026-08-11 that forum answers every request with an interactive Cloudflare “verify you are human” checkbox, so no unattended fetch gets through, and the Internet Archive has no copy of the thread or the files. Enri’s own site is unreachable from here and its archived index carries no RF or power sheet. The other thing a search turns up, an All About Circuits thread about a Famicom RF-box replacement PCB, is somebody’s new design with their own part choices and says nothing about the original.

No pins captured yet — bench stub.

+5V linear regulator (7805) 7805 / MC7805 / L7805CV, TO-220 HVC-CPU-07 · HVC-CPU-GPM · HVCN-CPU-01 · HVC-022/023 header-3^{single source}^{console5-fc,corpus}#

On the HVC-001 it is on the RF/power board, NOT the mainboard. On the AV Famicom it is U7 beside the DC plug

Standard TO-220 78xx pinning, IN / GND / OUT. The pin numbering below is the conventional order and is consistent with the schematic (9-10 V in, 5 V out), but I have not found a second explicit pin table for it in this family’s documentation, so it is tagged single-source. Modern drop-in: L7805CV or any reputable 5 V TO-220 78xx. Keep the heatsink.

The diagnostic that matters: roughly the input voltage on all three pins means the regulator has failed short and is passing its unregulated input straight to the logic. Usually with a burn mark to match. Replace the regulator, the fuse and at least one cap, and check what the over-voltage may have taken with it.

Designator trap on the AV Famicom: HVCN-CPU-01 silkscreens this part as U7 (marked I G O) right beside the DC plug. It is the regulator, not a buffer, and there is no U8 on that board.

Not applicable to the Twin Famicom, which uses an adjustable M5236L instead: see that card.

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Pin	Signal	Cat	Net	Note
1	IN	rail	vin	~10 V unregulated from the DC jack ^{single source}
2	GND	gnd	gnd	tab is also GND on a TO-220 78xx ^{single source}
3	OUT	rail	vcc	5.0 V to the board. ~10 V here too = failed short ^{single source}

+5V adjustable regulator (Twin Famicom) Mitsubishi M5236L: IC201 on the PWBF4785CEZZ power PCB, TO-92L AN-500/505 header-3^{single source}^{ds-m5236l,console5-tf,corpus}#

NOT a 7805, and NOT even a pass regulator: it is a control IC that drives an external PNP. R211 sets the +5V rail

The Twin Famicom does not use a fixed regulator. IC201 is a Mitsubishi M5236L general-purpose three-terminal variable output regulator, and R211 on the power PCB is the +5 V adjustment. Do not drop a fixed 7805 into that position without reworking the adjust network, and always re-set 5.00 V after touching the board: a Twin that reads 4.6 V is a trim job, not a dead regulator.

Pulling the Mitsubishi datasheet changed my read of this part in a way that matters on the bench. The M5236L is subtitled “(for driver)” and it is not in the load path at all: its absolute-maximum drive current is 30 mA and the datasheet’s own standard test circuit hangs an external PNP pass transistor (a 2SB524 in the example) off pin 1 through a 220 Ω base resistor, with the load current flowing emitter-to-collector around the IC. Feedback comes back to pin 3 from an R2/R1 divider on the output, and the internal reference is 1.26 V typical, so the output is Vo = 1.26 x (1 + R2/R1). It is a TO-92L three-pin part: the little black plastic thing next to it doing the actual work is the pass transistor.

Practical consequence: a Twin with no +5 V and an M5236L that measures “fine” is not proof the regulator is good, and equally the fault may not be the M5236L at all. Check the external pass transistor and the divider around R211 before condemning an obsolete IC you cannot buy. I have not had a PWBF4785CEZZ on the bench to identify Sharp’s pass device, so that part of the chain is uncaptured here.

The R211-adjusts-+5V mapping is Console5’s, single-source; the pin table and the external-PNP architecture are the Mitsubishi datasheet. The M5236L is long obsolete with no franchised stock; it is NOS or a donor board.

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Pin	Signal	Cat	Net	Note
1	INPUT / drive	rail	vin	supply pin AND the base-drive output for the external PNP: 30 mA absolute max, so it never carries the rail current ^{single source}
2	GND	gnd	gnd	reference for both the input-voltage and the Vref spec ^{single source}
3	VOLTAGE ADJUSTMENT	signal	adj	feedback from the output divider; 1.26 V typ. reference to pin 2. R211 lives on this node ^{single source}

Schematic facts

DC input: Famicom HVC-001 and AV Famicom HVC-101: DC 10 V, 850 mA, CENTRE-NEGATIVE, 5.5 / 2.1 mm barrel (adapter HVC-002) (the voltage and current are OEM; the polarity is secondary-sourced but four independent sources agree)^✓^{fc-manual,junkerhq,famicomworld-pwr,retrogamesupply}
notes
The OEM manual’s ratings page gives DC10V 850mA and about 4 W, and states no polarity glyph at all. An adversarial search for any centre-positive Famicom claim returned nothing.
DC input: Famicom Disk System: DC 9 V, 400 mA, CENTRE-NEGATIVE, 5.5 / 2.1 mm barrel (adapter HVC-025) (the 6x C-cell base is the 9 V equivalent; 400 mA will not carry a console)^✓^{junkerhq,famicomworld-fdspwr,fds-power05}
notes
The reverse-engineered FMD POWER-05 schematic independently annotates the barrel jack ‘Center negative’. Order the HVC-025 AC adapter, not the red battery base under the drive: they are different parts.
DC input: Sharp Twin Famicom: DC 7.6 V, 1.25 A, 5.5 / 2.5 mm barrel: POLARITY DISPUTED (at least one respected source lists it CENTRE-POSITIVE, the opposite of every other brick here. Meter it, every time)^{single source}^{junkerhq,corpus}
notes
This is an unresolved conflict in my own reference library and I am not going to paper over it. Also note the barrel is 2.5 mm, so a 2.1 mm Famicom plug makes intermittent contact in a Twin. And the OEM Twin brick is 100 V mains.
AC input: PAL NES-001: 9 to 9.8 V AC, 1.3 A, no polarity (rectified by an onboard bridge) (do NOT carry Famicom DC/polarity logic onto a PAL NES, or the reverse)^{single source}^junkerhq
notes
PAL units also tend to have a blue socket with a larger barrel than NTSC despite identical power requirements: an NTSC NES PSU will not physically seat. Check the plug fits before diagnosing ‘dead’.
Logic rail: 5.0 V DC (on an HVC-001 probe it at P3 pins 2/3: the regulator is on the RF/power board)^✓^{fc-oem,corpus}
Master clock: NTSC-J (Famicom, AV Famicom, Twin): 21.477272 MHz (X1); CPU 1.789773 MHz after the 2A03's divide-by-12 (60 Hz, 262 lines (exact refresh 60.0988 Hz))^✓^{nesdev-cpu,nesdev-ppu,corpus}
Master clock: PAL: 26.6017125 MHz; CPU 1.662607 MHz after the 2A07's divide-by-16 (50 Hz, 312 lines (exact refresh 50.0070 Hz))^✓^{nesdev-pal,consolemods-region,corpus}
notes
Nintendo divided by 16 rather than 15 to keep the Johnson-counter structure, which needs an even period. That is why PAL runs about 7 percent slow rather than at NTSC-equivalent speed; the Dendy famiclones divide by 15 instead.
PPU reset pin on every Famicom: PPU pin 22 tied hard to +5 V (the screen does not clear when you hold Reset: that is stock, not a fault)^✓^{nesdev-ppu,nocash,enri}
60-pin vs 72-pin cartridge bus: 60-pin adds cart audio (45/46) and CartridgePresent (31); 72-pin adds CIC, EXP0-9 and SYSTEM CLK but DROPS cart audio (this is the hardware reason expansion audio plays on a Famicom and is silent on a stock NES)^✓^{nesdev-cart,consolemods-region}
Cartridge connector pitch: 60-pin = 2.54 mm (0.1 in, standard stock fits); 72-pin = 2.50 mm (NOT 0.1 in, standard stock does NOT fit) (the 2.50 mm error accumulates over 36 positions and shorts pins near the card ends)^✓^{nesdev-cart,corpus}
Region lockout: Famicom family: NONE. No 60-pin console can host a lock CIC at all: the 60-pin bus carries no CIC clock, data or reset lines (HVC-001, HVC-101 and the Twin Famicom are region-free structurally, not by omission)^✓^{nesdev-cic,nesdev-cart,consolemods-region}
notes
The lone Famicom-family exception is the FamicomBox / Sharp FamicomStation, which uses modified 72-pin carts and does carry a CIC (3198).
CIC region codes (front-loaders only): 3193 / 6113 = NTSC · 3197 = PAL-A (GBR, UKV, AUS, ITA) · 3195 = PAL-B (NOE, FRA, EEC, ESP, SCN, and KOR) · 3196 = Asia · 3198 = FamicomBox (real chips carry a letter suffix: expect 3197A, 3195A, 3196A on the 10NES near the RF box)^✓^{nesdev-cic,consolemods-region}
notes
PAL-A and PAL-B carts are mutually incompatible without defeating the console CIC; European boxes carry a large A or B for this reason. The PAL-B list is not exhaustive: FRG, HOL, GPS and SWE map there too.
The Korean Comboy trap: Hyundai Comboy HGM-2000 = NTSC internals (2A03 / 2C02, 60 Hz) with a PAL-B 3195 CIC (it refuses US carts on lockout while running at NTSC speed: not a PAL unit, not a dead CIC)^{single source}^{consolemods-region}
notes
Inverse trap: PAL-B carts DO pass lockout on a Comboy, then run about 20 percent fast on the NTSC clock. A passing lockout check is not proof of correct timing.
How to identify a PAL board: By the silicon, never by the silkscreen: RP2A07 + RP2C07 + 26.6 MHz crystal (Nintendo used the same NES-CPU-xx board ladder for every region)^✓^{consolemods-region,corpus}
notes
A full region swap is more than the four obvious parts: CPU, PPU, crystal and CIC, PLUS the RF modulator (which is region-specific) and the controller-port diode population. And a converted console is not bit-identical to a factory unit: the 2C07 has a 71-scanline VBlank and swapped red/green emphasis, and the 2A07 runs its APU frame counter at 50 Hz.
FDS ERR.02: BIOS: 'No disk power supply. Batteries and/or AC adaptor' (bench-practical: weak batteries or supply, OR the belt has slipped off the motor pulley)^✓^{famicomworld-err,diskspec}
notes
An ERR.02 that clears on a fresh supply is a battery problem, not a drive problem. HVC-025 is only 400 mA, and a sagging supply shows up as a drive that spins down mid-load.
FDS ERR.21: BIOS: 'Disk card header block (NINTENDO-HVC) wrong' (the drive cannot find the start of the data: prove the media BEFORE touching an alignment screw)^✓^{famicomworld-err,diskspec,fds-belt}
notes
ERR.21 and ERR.22 mean the drive never found the start; ERR.23 through ERR.25 mean it got past the disk header and is losing data further into the spiral. The head-alignment technique everyone uses is to step the head in one direction until ERR.21 flips to ERR.22, which marks one boundary of the good window, then reverse and bracket back to the centre.
FDS ERR.27: BIOS: 'Block end mark seen but ends prematurely' (the '27 = worn pressure pad' rule is a bench heuristic, not what the ROM means)^✓^{famicomworld-err,diskspec,fds-belt}
notes
Worth being precise about, because the two published readings of the FDS error list do not fully agree. The BIOS meaning is a plain read/CRC failure. The repair community maps ERR.27 to a worn or thin cotton-felt pressure pad, or to spindle-motor calibration. Both are worth checking; only one is what the code literally says.
FDS drive speed target: 400 RPM at the disk-table shaft (about 800 RPM at the motor belt holder) (treat any 800-900 RPM reading AT THE SHAFT as a stroboscope harmonic: the older 820/873 RPM figures were retracted by their own author)^{single source}^{tinkerdifferent}
notes
The retraction is explicit: ‘I discovered the stroboscope app I was using made it easy to have a ~2x factor error. I had previously reported that the RPM was 873RPM however I can confidently say it is 400 RPM.’ Calibrate with a real tachometer.
FDS head alignment target: 10.68 to 10.72 mm between the metal outcroppings, about ±0.05 mm working tolerance (a quarter turn of the HEAD screw moves it about 0.1 mm: work in eighth turns)^✓^{fds-belt,tinkerdifferent}
notes
Adjust at the head screw only. Never touch the disk-clamp or spindle set screw on a factory-aligned drive. Scrape the locking glue off the head screw with an exactly-fitting driver first or you will strip it.
AV Famicom video output: Composite only: Multi Out pin 9 plus mono audio on 11/12 (the RGB, CSYNC and S-video pins exist in the shell but are not connected. You cannot wire your way to RGB)^✓^{nerdly-av,consolemods-multiout,superfamicom-multiout}
Famicom audio mixer (OEM values): R4 = 20K from CPU pin 1, R5 = 12K from CPU pin 2, 100 Ω to ground on each, C2 = 1 µF into a 40H368 inverter with R7 = 100K feedback (reference values when a 'quiet channel' turns out to be a drifted resistor)^✓^{fc-oem,nerdly-audio}
notes
Board-revision caveat: the later GPM boards are reported to drop R7 to 43K, cutting internal 2A03 gain, so a GPM Famicom sounds like its expansion audio is too loud. That 43K figure is single-source: meter R7 before lifting it. On a GPM board, loud expansion audio is stock behaviour.
FDS expansion audio level: roughly 2.4x the maximum volume of an APU square channel, lowpassed around 2 kHz (an FDS game noticeably louder than the base channels is normal, not a fault)^{single source}^corpus

Reference confidence key

How to read the confidence tags and source citations on the data above. Note there are no bench tags on this page, and that is deliberate.

Sources

board-scans: archive.org 'Nintendo Famicom Motherboard Scans': high-res bare-board scans of HVC-CPU-05, HVC-CPU-07 (x2), HVC-CPU-GPM-02 and HVCN-CPU-01
console5-fc: Console5 TechWiki: Famicom (wiki.console5.com/wiki/Famicom). HVC-CPU-07 / GPM-02 / HVCN-CPU-01 chip lists and capacitor lists, HVC-002 adapter cap
console5-fds: Console5 TechWiki: Famicom Disk System (wiki.console5.com/wiki/Famicom_Disk_System). HVC-FMR-03 and FMD POWER-0x chip lists, cap lists, drive alignment procedure
console5-tf: Console5 TechWiki: Twin Famicom (wiki.console5.com/wiki/Twin_Famicom). PWBF4785CEZZ / DUNTK5630DE / SP-394HB chip lists, cap maps, supply connector J and K pinouts, R211 adjust
consolemods-md: ConsoleMods Wiki: NES model differences (consolemods.org/wiki/NES:NES_Model_Differences). Famicom board-revision ladder, GPM changes, AV Famicom JIO integration
consolemods-multiout: ConsoleMods Wiki: Nintendo Multi Out (consolemods.org/wiki/Nintendo_Multi_Out). 12-pin Multi Out pinout and per-console signal table
consolemods-region: ConsoleMods Wiki: NES region information (consolemods.org/wiki/NES:Region_Information). CIC region codes, PAL silicon, PAL DC jack
corpus: My own Famicom-family reference library (offline research corpus): the adversarial verification log behind the claims on this page
diskspec: Kevin Horton, FDS disk-format spec (nesdev.org/diskspec.txt): independent corroboration of the BIOS error list and the header/file block numbering
ds-cd4069ub: Texas Instruments CD4069UB CMOS Hex Inverter datasheet, SCHS054E (November 1998, revised January 2019): CD4069UB Functional Diagram, incl. the VDD = pin 14 / VSS = pin 7 note
ds-m5236l: Mitsubishi Linear ICs M5236L / M5236ML 'General Purpose 3-Terminal Variable Voltage Output Regulator (For Driver)' datasheet, pp. 4-26 to 4-28: PIN CONFIGURATION / PIN CONNECTION block, electrical-characteristics table and standard test circuit (a)
ds-mb8416a: Fujitsu MB8416A-12 / MB8416A-15 'CMOS 16,384-Bit Static Random Access Memory' datasheet (Advance Information, Fujitsu Microelectronics): PIN ASSIGNMENT diagram and the mode truth table's pin-number row
ds-tmm2015bp: Toshiba MOS Memory Products TMM2015BP-90 / -12 / -10 / -15 '2,048 WORD x 8 BIT STATIC RAM' datasheet, sheet B-3: PIN CONNECTION (top view) and PIN NAMES table
enri: Enri / Narr redrawn Famicom schematics (archive.org, 'Comprehensive Famicom Schematics'): CPU, PPU, RAM, cart connector, joypad + DA-15, control pads / 4021 / RF / power sheets
famicomworld-err: Famicom World: Disk System error messages (famicomworld.com/workshop/tech/disk-system-error-messages/). BIOS-literal ERR.01-31 list
famicomworld-fdspwr: Famicom World: Disk System power adaptor (famicomworld.com/workshop/tech/disk-system-power-adaptor/). HVC-025 rating and battery equivalent
famicomworld-pwr: Famicom World: Famicom power adaptor (famicomworld.com/workshop/tech/famicom-power-adaptor/). HVC-002 label transcription
fc-manual: Nintendo Family Computer HVC-001 owner's manual (Japanese, 改訂版4), archive.org: p.16 §7 定格 ratings block: DC10V 850mA, ~4 W, adapter HVC-002. States no polarity
fc-oem: Nintendo factory 'CPU基板回路図' Famicom mainboard schematic, OEM scan (archive.org, 'Comprehensive Famicom Schematics'): P1 60-pin table, P3 harness table, audio mixer, video buffer
fds-belt: famicomdisksystem.com: FDS belt replacement and adjustment tutorial. The four adjustments, head spacing 10.68-10.72 mm, worn felt pad → ERR.27
fds-power05: Shibesoft AS reverse-engineered KiCad schematic of the FDS FMD POWER-05 board (2018-10-01), via Console5: center-negative barrel jack, AN1358, VR1 motor-speed pot, BU3208, 12-pin drive connector
junkerhq: junkerhq.net, The Console Power Supply Bible: per-console PSU voltage, current, polarity and barrel-size table
mic-schematic: Famicom controller-2 microphone schematic rev 6 / rev 7B (Flashback Vintage Electronics), archive.org: mic capsule, 2.2 kΩ bias, 0.33 µF coupling, 4069 amp
nerdly-audio: Nerdly Pleasures: 'Famicom & NES: Simple Tweaks to Restore Audio Balance Levels' (nerdlypleasures.blogspot.com, 2018-01). Famicom mixer values, GPM R7 change, AV Famicom R14
nerdly-av: Nerdly Pleasures: 'Famicom AV: Issues and Solutions' (nerdlypleasures.blogspot.com, 2014-10). HVC-101 composite-only Multi Out, mono audio, controller ports omit D3/D4, 10 V DC 850 mA center-negative
nesdev-cart: NESdev Wiki: Cartridge connector (nesdev.org/wiki/Cartridge_connector). 60-pin Famicom and 72-pin NES pin tables
nesdev-cic: NESdev Wiki: CIC lockout chip (nesdev.org/wiki/CIC_lockout_chip). Region code table
nesdev-cpu: NESdev Wiki: CPU pinout (nesdev.org/wiki/CPU_pinout). RP2A03 / RP2A07 40-pin DIP
nesdev-ctrl: NESdev Wiki: Controller port pinout (nesdev.org/wiki/Controller_port_pinout). NES 7-pin port, protection diodes, OEM wire colours
nesdev-exp: NESdev Wiki: Expansion port (nesdev.org/wiki/Expansion_port). Famicom DA-15 and NES 48-pin
nesdev-jio: NESdev Wiki: BU3266 / BU3270 pinout (nesdev.org/wiki/BU3266_/_BU3270_pinout). Nintendo custom PIO, 32-pin DIP (retrieved 2026-07-26)
nesdev-pal: NESdev Wiki: PAL video (nesdev.org/wiki/PAL_video). 50 Hz / 312-line timing, PAL master clock
nesdev-ppu: NESdev Wiki: PPU pinout (nesdev.org/wiki/PPU_pinout). Composite RP2C02 / RP2C07 40-pin DIP
nesdev-ppuvar: NESdev Wiki: PPU variants (nesdev.org/wiki/PPU_variants). 2C02/2C07 sub-revisions, RGB PPUs
nocash: Martin Korth, 'Everynes' NES/Famicom hardware specs (problemkaputt.de/everynes.htm): independent 2A03 / 2C02 / 60-pin / 72-pin / DA-15 / 7-pin controller pin tables
retrogamesupply: RetroGameSupply: Power Supply for Nintendo Famicom AV. Modern regulated HVC-002 replacement, 9 V / 1.5 A center-negative
schenkzoola: schenkzoola's KiCad Famicom HVC-001 mainboard schematic (github.com/schenkzoola/NES, CC BY-SA 4.0, rev 1.0 2020-07-04): a redraw with reference designators and pin numbers that its author checked against the factory schematic. Draws the P3 'RF Modulator' harness and the Q1 2SA937 video buffer with values, retrieved 2026-08-11
superfamicom-multiout: superfamicom.org wiki: AV Multi Out pinout (wiki.superfamicom.org/av-multiout-pinout). 12-pin Multi Out pinout
tinkerdifferent: TinkerDifferent: Famicom FDS drive calibration (WIP updates, 2022-09). Corrected 400 RPM disk-table target, ±0.05 mm head tolerance, retraction of the earlier 820/873 RPM figures
wikimedia-av: Wikimedia Commons: Nintendo AV Famicom motherboard photos by Evan-Amos (public domain). Populated HVCN-CPU-01, laser-marked 'JIO A BU3270S'

Confidence: verified two+ sources agree · single source one source / scan-derived, treat with care · bench my own measurement or practice.

Sources and further reading

These are the outside references I trust for the Famicom family and PAL NES. I link them rather than copy them, and where a source is a community schematic redraw or a photo I link it rather than reproducing the image.